Quick Spec:

Part Number: 400GBase-LR8-QSFP56-DD 400GBase-LR8-QSFP56-DD-EXT

400GBase-LR8-QSFP56-DD-IND

Form Factor: QSFP56-DD

TX Wavelength: 1310nm

Reach: 10km

Cable Type: SMF

Rate Category: 400GBase

Interface Type: LR8

DDM: Yes

Connector Type: Dual-LC

Features

• 8 channels full-duplex transceiver modules

• Transmission data rate up to 53Gbps per channel

• 8x53Gbps PAM4 transmitter and PAM4 receiver

• 8 channels LAN-WDM

• 8 wavelengths EML

• 8 channels PIN photo detector

• Internal CDR circuits on both receiver and transmitter channels

• Power consumption <12.5W

• Hot Pluggable QSFP DD form factor and Compliant with CMIS 4.0

• Maximum link length of 10km G.652 SMF with KP-FEC

• Duplex LC receptacles

• Built-in digital diagnostic functions

• Operating case temperature 0°C to +70°C

• 3.3V power supply voltage

• RoHS compliant (lead free)

• Operating Case Temperature

  Standard: 0°C to +70 °C Extended -5°C to +85 °C Industrial -40°C to +85 °C

  
  

  Applications

• IEEE 802.3bs 400GBASE-LR8

  Description

  The FluxLight 400GBASE-LR8-QSFP56-DD is an Eight-Channel, Pluggable, Parallel, Fiber-Optic QSFP Double Density for 400 Gigabit Ethernet Applications. This transceiver is a high-performance module for 10km multi-lane data communication and interconnection applications. It integrates eight data lanes in each direction with 8x26.5625GBd. Each lane can operate at 53.125Gbps up to 10km using G.652 SMF with KP-FEC. These modules are designed to operate over single mode fiber systems using LAN-WDM 8 wavelengths. The electrical interface uses a 76 contact edge type connector. The optical interface uses duplex LC connector. The Common Management Interface Specification (CMIS) for QSFP DD modules, this module incorporates FluxLight Technologies proven circuit and EML technology to provide reliable long life, high performance, and consistent service.

  
  

  

  
  

  Figure1. Module Block Diagram

  
  

  Absolute Maximum Ratings

  
  

  Parameter	Symbol	Min	Max	Unit
  Supply Voltage	Vcc	-0.3	3.6	V
  Input Voltage	Vin	-0.3	Vcc+0.3	V
  Storage Temperature	Tst	-20	85	ºC
  Case Operating Temperature	Top	0	70	ºC
  Humidity(non-condensing)	Rh	5	95	%

  Recommended Operating Conditions

  
  

  Parameter	Symbol	Min	Typical	Max	Unit
  Supply Voltage	Vcc	3.13	3.3	3.47	V
  Operating Case temperature	Tca	0		70	ºC
  Data Rate Per Lane	fd		26.5625		GBd
  Humidity	Rh	5		85	%
  Power Dissipation	Pm			12.5	W

  
  

  Electrical Specifications

  
  

  Parameter	Symbol	Min	Typical	Max	Unit
  Differential input impedance	Zin	90	100	110	ohm
  Differential Output impedance	Zout	90	100	110	ohm
  Differential input voltage amplitude	ΔVin			900	mVp-p
  Differential output voltage amplitude	ΔVout			900	mVp-p
  Skew	Sw			300	ps
  Bit Error Rate	BER			2.4E-4	-
  Near-end Eye Width at 10^-6 probability(EW6)		0.265			UI
  Near-end Eye Height at 10^-6 probability(EH6)		70			mV
  Far-end Eye Width at 10^-6 probability(EW6)		0.20			UI
  Far-end Eye Height at 10^-6 probability(EH6)		30			mV
  Near-end Eye Linearity		0.85			-

  Note：

  1. BER=2.4E-4; PRBS31Q@26.5625GBd. Pre-FEC

  2. Differential input voltage amplitude is measured between TxnP and TxnN.

  3. Differential output voltage amplitude is measured between RxnP and RxnN.

Optical Characteristics-Transmitter

Table 3 - Optical Characteristics

Optical Characteristics-Receiver

Note：

1．Measured with conformance test signal at TP3 for BER = 2.4E-4 Pre-FEC

Pin Description

Figure2. Electrical Pin-out Details

ModSelL Pin

The ModSelL is an input signal that shall be pulled to Vcc in the QSFP56-DD module. When held low by the host, the module responds to 2-wire serial communication commands. The ModSelL allows the use of multiple QSFP56-DD modules on a single 2-wire interface bus. When ModSelL is “High”, the module shall not respond to or acknowledge any 2-wire interface communication from the host.

In order to avoid conflicts, the host system shall not attempt 2-wire interface communications within the ModSelL de-assert time after any QSFP56-DD modules are deselected. Similarly, the host must wait at least for the period of the ModSelL assert time before communicating with the newly selected module. The assertion and de-asserting periods of different modules may overlap as long as the above timing requirements are met.

ResetL Pin

The ResetL signal shall be pulled to Vcc in the module. A low level on the ResetL signal for longer than the minimum pulse length (t_Reset_init) initiates a complete module reset, returning all user module settings to their default state.

LPMode Pin

LPMode is an input signal. The LPMode signal shall be pulled up to Vcc in the QSFP56-DD module. LPMode is used in the control of the module power mode. See CMIS Section 6.3.1.3.

ModPrsL Pin

ModPrsL shall be pulled up to Vcc Host on the host board and pulled low in the module. The ModPrsL is asserted “Low” when the module is inserted. The ModPrsL is deasserted “High” when the module is physically absent from the host connector due to the pull-up resistor on the host board.

IntL Pin

IntL is an output signal. The IntL signal is an open collector output and shall be pulled to Vcc Host on the host board. When the IntL signal is asserted Low it indicates a change in module state, a possible module operational fault or a status critical to the host system. The host identifies the source of the interrupt using the 2-wire serial interface. The IntL signal is deasserted “High” after all set interrupt flags are read.

Power Supply Filtering

The host board should use the power supply filtering shown in Figure 3.

Figure 3. Host Board Power Supply Filtering

Diagnostic Monitoring Interface

Digital diagnostics monitoring function is available on all FluxLight QSFP DD products. A 2-wire serial interface provides user to contact with module.

Memory Structure and Mapping

This limits the management memory that can be directly accessed by the host to 256 bytes, which is divided in Lower Memory (addresses 00h through 7Fh) and Upper Memory (addresses 80h through FFh).

A larger addressable management memory is required for all but the most basic modules. This is supported by a structure of 128-byte pages, together with a mechanism for dynamically mapping any of the 128-byte pages from a larger internal management memory space into Upper Memory the host addressable space.

The addressing structure of the additional internal management memory2 is shown in Figure 8-2. The management memory inside the module is arranged as a unique and always host accessible address space of 128 bytes (Lower Memory) and as multiple upper address subspaces of 128 bytes each (Pages), only one of which is selected as host visible in Upper Memory. A second level of Page selection is possible for Pages for which several instances exist (e.g. where a bank of pages with the same Page number exists).

This structure supports a flat 256 byte memory for passive copper modules and permits timely access to addresses in the Lower Memory, e.g. Flags and Monitors. Less time critical entries, e.g. serial ID information and threshold settings, are available with the Page Select function in the Lower Page. For more complex modules which require a larger amount of management memory the host needs to use dynamic mapping of the various Pages into the host addressable Upper Memory address space, whenever needed.

Note: The management memory map has been designed largely after the QSFP memory map. This memory map has been changed in order to accommodate 8 electrical lanes and to limit the required memory space. The single address approach is used as found in QSFP. Paging is used in order to enable time critical interactions between host and module.

Supported Pages

A basic 256 byte subset of the Management Memory Map is mandatory for all CMIS compliant devices. Other parts are only available for paged memory modules, or when advertised by the module. See CMIS V4.0 for details regarding the advertisement of supported management memory spaces.

Support of the Lower Memory and of Page 00h is required for all modules, including passive copper cables. These pages are therefore always implemented. Additional support for Pages 01h, 02h and bank 0 of Pages 10h and 11h is required for all paged memory modules.

Bank 0 of pages 10h-1Fh, provides lane-specific registers for the first 8 lanes, and each additional bank provides support for additional 8 lanes. Note, however, that the allocation of information over the banks may be page specific and may not to be related to grouping data for 8 lanes.

The structure allows address space expansion for certain types of modules by allocating additional Pages. Moreover, additional banks of pages.

Figure 5. QSFP DD Memory Map

Mechanical Dimensions

Figure6. Mechanical Specifications

ESD

This transceiver is specified as ESD threshold 1kV for high speed data pins and 2kV for all other electrical input pins, tested per MIL-STD-883, Method 3015.4 /JESD22- A114-A (HBM). However, normal ESD precautions are still required during the handling of this module. This transceiver is shipped in ESD protective packaging. It should be removed from the packaging and handled only in an ESD protected environment.

Laser Safety

This is a Class 1 Laser Product according to EN 60825-1:2014. This product complies with 21 CFR 1040.10 and 1040.11 except for deviations pursuant to Laser Notice No. 50, dated (June 24, 2007).

Caution: Use of controls or adjustments or performance of procedures other than those specified herein may result in hazardous radiation exposure.

Licensing

The following U.S. patents are licensed by Finisar to FluxLight, Inc.:

U.S. Patent Nos: 7,184,668, 7,079,775, 6,957,021, 7,058,310, 6,952,531, 7,162,160, 7,050,720