Arista Compatible QDD-400G-SR4.2-A-FL Quick Spec:

Part Number: QDD-400G-SR4.2-A-FL QDD-400G-SR4.2-A-EXT-FL QDD-400G-SR4.2-A-IND-FL

Form Factor: QSFP56-DD

TX Wavelength: BiDi 850nm/908nm

Reach: 150m

Cable Type: MMF

Rate Category: 400GBase

Interface Type: SR4.2

DDM: Yes

Connector Type: MPO-12

Arista Compatible QDD-400G-SR4.2-A-FL Features

• QSFP56-DD MSA compliant

• 8 Bi-Directional Optical Lanes

• IEEE802.3bs Specification compliant

• Up to 150m transmission on OM5 Multimode Fiber

• 8x53.125Gb/s electrical interface (400GAUI-8)

• Maximum power consumption 12W

• MPO-12 connector

• RoHS compliant

• Operating Case Temperature

  • Standard: 0°C to +70 °C

  • Extended -5°C to +85 °C

  • Industrial -40°C to +85 °C

    Arista Compatible QDD-400G-SR4.2-A-FL Applications

• 400G Ethernet

• Infiniband interconnects

• Datacenter Enterprise networking

Arista Compatible QDD-400G-SR4.2-A-FL General Description

This product can support 400Gb/s bit rates. It is a parallel Quad Small Form-factor Pluggable—double density (QSFP-DD) Bi-Directional optical module. The module accepts eight host electrical data and transmits them in two groups of optical bi-directional lanes (each group contains 4 pairs of optical lane) to allow optical communication over optical multi-mode fibers. Reversely, on the receiver side, the module accepts 8 sets of optical input signal and converts them to 8 channels of electrical data.

An optical fiber with an MPO-12 connector can be plugged into the QSFP-DD module receptacle. Proper alignment is ensured by the guide pins inside the receptacle. The cable usually cannot be twisted for proper channel to channel alignment. Electrical connection is achieved through an MSA-compliant 76-pin edge type connector.

The module operates by a single +3.3 V power supply. LVCMOS/LVTTL global control signals, such as Module Present, Reset, Interrupt and Low Power Mode, are available with the modules. A 2-wire serial interface is available to send and receive more complex control signals, and to receive digital diagnostic information. Individual channels can be addressed and unused channels can be shut down for maximum design flexibility.

The product is designed with form factor, optical/electrical connection and digital diagnostic interface according to

the QSFP56 Multi-Source Agreement (MSA). It has been designed to meet the harshest external operating conditions including temperature, humidity and EMI interference. The module offers very high functionality and feature integration, accessible via a two-wire serial interface.

Arista Compatible QDD-400G-SR4.2-A-FL Functional Description

This product can support 425Gb/s bit rates. It is a parallel Quad Small Form-factor Pluggable—double density (QSFP-DD) Bi-Direction optical module. The module converts eight host electrical data into two groups of optical bi-directional lanes (each group contains 4 pairs of optical lane) to allow optical communication over optical multi- mode fibers. The transmitter of first group is 850 nm VCSEL basis, it is 908 nm VCSEL basis for the second group. On the receiver side, the module accepts 8 sets of optical input signal and transmits them to 8 channels of electrical data. The receiver module outputs electrical signals are also voltage compatible with Common Mode Logic (CML) levels.

This product is allowed for two typical applications: The first application is QSFP-DD SR4.2 to QSFP-DD SR4.2 point to point communication. The second application is QSFP-DD SR4.2 to 4 x QSFP28 SR1 .2 breakout communication. Figure 1 shows the functional block diagram of this product.

A single + 3.3 V power supply is required to power up this product. All the power supply pins are internally connected and should be applied concurrently. As per MSA specifications the module offers seven low speed hardware control pins (including the 2 -wire serial interface): ModSelL, SCL, SDA, ResetL, InitMode, ModPrsL and IntL.

Module Select (ModSelL) is an input pin. When held low by the host, this product responds to 2-wire

serial communication commands. The ModSelL allows the use of this product on a single 2 -wire interface bus – individual ModSelL lines must be used.

Serial Clock (SCL) and Serial Data (SDA) are required for the 2-wire serial bus communication interface and enable the host to access the memory map.

The ResetL pin enables a complete reset, returning the settings to their default state, when a low level on the ResetL pin is held for longer than the minimum pulse length. During the execution of a reset the host shall disregard all status bits until it indicates a completion of the reset interrupt. The product indicates this by posting an IntL (Interrupt) signal with the Data_Not_Ready bit negated in the memory map. Note that on power up (including hot insertion) the module should post this completion of reset interrupt without requiring a reset.

Initialize Mode (InitMode) is an input signal. It is pulled up to Vcc in the QSFP-DD module. The InitMode signal allows the host to define whether the QSFP-DD module will initialize under host software control (InitMode asserted High) or module hardware control (InitMode deasserted Low). Under host software control, the module shall remain in Low Power Mode until software enables the transition to High Power Mode, as defined in the QSFP-DD Management Interface Specification. Under hardware control (InitMode de-asserted Low), the module may immediately transition to High Power Mode after the management interface is initialized. The host shall not change the state of this signal while the module is present. In legacy QSFP applications, this signal is named LPMode. See SFF-8679 for LPMode signal description.

Module Present (ModPrsL) is a signal local to the host board which, in the absence of a product, is normally pulled up to the host Vcc. When the product is inserted into the connector, it completes the path to ground through a resistor on the host board and asserts the signal. ModPrsL then indicates its present by setting ModPrsL to a “Low” state.

Interrupt (IntL) is an output pin. “Low” indicates a possible operational fault or a status critical to the host system. The host identifies the source of the interrupt using the 2-wire serial interface. The IntL pin is an open collector output and must be pulled to the Host Vcc voltage on the Host board.

Transceiver Block Diagram

Figure 1. Transceiver Block Diagram

Pin Assignment and Description

The electrical pinout of the QSFP56-DD module is shown in Figure 2 below.

Figure 2. MSA Compliant Connector

Pin Definition

Optical Interface Lanes and Assignment

Figure 3 shows the orientation of the multi-mode fiber facets of the optical connector. Table 1 provides the lane assignment.

Figure 3. Outside View of the QSFPDD MPO-12 Receptacle

Recommended Power Supply Filter

Absolute Maximum Ratings

It has to be noted that the operation in excess of any individual absolute maximum ratings might cause permanent damage to this module.

Recommended Operating Conditions and Power Supply Requirements

Notes:

1. FEC provided by host system.

2. FEC required on host system to support maximum distance.

Electrical Characteristics

The following electrical characteristics are defined over the Recommended Operating Environment unless otherwise specified.

Notes:

1. With the exception to IEEE 802.3bs 120E.3.1.2 that the pattern is PRBS31Q or scrambled idle.

2. Meets BER specified in IEEE 802.3bs 120E.1.1.

3. DC common mode voltage generated by the host. Specification includes effectsof ground offset voltage.

Optical Characteristics

Notes:

1. Average launch power, each lane (min) is informative and not the principal indicator of signal strength. A transmitter with launch power below this value cannot be compliant; however, a value above this does not ensure compliance.

2. Even if the TDECQ < 1.4 dB, the OMAouter (min) must exceed this value.

3. TDECq is specified and measured as per IEEE802.3.cm Clause 150.8.5.

4. Ceq is a coefficient defined in IEEE 802.3-2018 Clause 121.8.5.8, which accounts for the reference equalizer noise enhancement.

5. If measured into type A1a.2, or type A1a.3, or type A1a.4, 50 um fibers in accordance with IEC 61280-1-4.

6. The receiver shall be able to tolerate, without damage, continuous exposure to an optical input signal having this average power level on one lane. The receiver does not have to operate correctly at this input power.

7. Average receive power, each lane (min) is informative and not the principal indicator of signal strength. A received power below this value cannot be compliant; however, a value above this does not ensure compliance.

8. Measured with a conformance test signal at TP3 (see IEEE 802.3 Cl 150 ) for the BER specified. They are not characteristics of the receiver. The conditions for measuring stressed receiver sensitivity are the following:

   Stressed eye closure (SECQ), lane under test	4.5	dB
   SECQ – 10log10(Ceq) lane under test (max)	4.5	dBm
   OMAouter of each aggressor lane	3.0	dBm

   These test conditions are for measuring stressed receiver sensitivity.

9. Receiver sensitivity is considered a normative requirement. RX sensitivity is defined for a transmitter with a value of SECQ up to 4.5dB. For transmitter with SECQ different from 4.5dB, limit is reported as per figure 5

   
   

   
   

   

   
   

   Figure 5. RX sensitivity

   
   

   Digital Diagnostic Functions

   The following digital diagnostic characteristics are defined over the normal operating conditions unless otherwise specified.

   
   

   Parameter	Symbol	Min	Max	Units	Notes
   Temperature monitor absolute error	DMI_Temp	-3	3	degC	Over operating temperature range
   Supply voltage monitor absolute error	DMI _VCC	-0.1	0.1	V	Over full operating range
   Channel RX power monitor absolute error	DMI_RX_Ch	-2	2	dB	1
   Channel Bias current monitor	DMI_Ibias_Ch	- 10%	10%	mA
   Channel TX power monitor absolute error	DMI_TX_Ch	-2	2	dB	1

   
   

   Notes:

   1. Due to measurement accuracy of different single mode fibers, there could be an additional +/-1 dB fluctuation, or a +/- 3 dB total accuracy.

Mechanical Dimensions

ESD

This transceiver is specified as ESD threshold 1kV for high speed data pins and 2kV for all others electrical input pins, tested per MIL-STD-883, Method 3015.4 /JESD22-A114-A (HBM). However, normal ESD precautions are still required during the handling of this module. This transceiver is shipped in ESD protective packaging. It should be removed from the packaging and handled only in an ESD protected environment.

Laser Safety

This is a Class 1M Laser Product according to EN 60825-1:2014. This product complies with 21 CFR 1040.10 except for deviations pursuant to Laser Notice No. 50, dated (June 24, 2007).

Caution: Use of controls or adjustments or performance of procedures other than those specified herein may result in hazardous radiation exposure.

Licensing

The following U.S. patents are licensed by Finisar to FluxLight, Inc.:

U.S. Patent Nos: 7,184,668, 7,079,775, 6,957,021, 7,058,310, 6,952,531, 7,162,160, 7,050,720