Cisco Compatible QDD-4X100G-FR-S-FL Quick Spec:

Part Number: QDD-4X100G-FR-S-FL QDD-4X100G-FR-S-EXT-FL QDD-4X100G-FR-S-IND-FL

Form Factor: QSFP56-DD

TX Wavelength: 1310nm

Reach: 2km

Cable Type: SMF

Rate Category: 400GBase

Interface Type: 4X100G-FR1

DDM: Yes

Connector Type: MPO-12

Cisco Compatible QDD-4X100G-FR-S-FL Features

• QSFP56-DD MSA compliant

• Parallel 4 Optical Lanes

• 100G Single Lambda MSA 100G-FR compliant

• Up to 2km transmission on single mode fiber (SMF) with FEC

• 8x53.125Gb/s electrical interface (400GAUI-8)

• Data Rate 106.25Gbps (PAM4) per channel.

• Maximum power consumption 12W

• MPO-12 connector

• RoHS compliant

• Operating Case Temperature

  • Standard: 0°C to +70 °C

  • Extended -5°C to +85 °C

  • Industrial -40°C to +85 °C

    Cisco Compatible QDD-4X100G-FR-S-FL Applications

• 400G Ethernet

• Infiniband interconnects

• Datacenter Enterprise networking

Cisco Compatible QDD-4X100G-FR-S-FL General Description

This product is a 400Gb/s Quad Small Form Factor Pluggable-double density (QSFP-DD) optical module designed for 2km optical communication applications. The module converts 8 channels of 50Gb/s (PAM4) electrical input data to 4 channels of parallel optical signals, each capable of 100Gb/s operation for an aggregate data rate of 400Gb/s. Reversely, on the receiver side, the module converts 4 channels of parallel optical signals of 100Gb/s each channel for an aggregate data rate of 400Gb/s into 8 channels of 50Gb/s (PAM4) electrical output data.

An optical fiber cable with an MTP/MPO-12 connector can be plugged into the QSFP-DD DR4 module receptacle. Proper alignment is ensured by the guide pins inside the receptacle. The cable usually cannot be twisted for proper channel to channel alignment. Electrical connection is achieved through a QSFP-DD MSA-compliant edge type connector.

The product is designed with form factor, optical/electrical connection and digital diagnostic interface according to the QSFP-DD Multi-Source Agreement (MSA) Type 2. It has been designed to meet the harshest external operating conditions including temperature, humidity and EMI interference.

QSFP56-DD-4X100G-FR1 Functional Description

The module incorporates 4 parallel channels on 1310nm center wavelength, operating at 100G per channel. The transmitter path incorporates a quad channel EML driver together with 4 parallel EMLs. On the receiver path, a PD array is connected with a quad channel TIA to convert the parallel 400Gb/s optical input into 4 channels of parallel 100Gb/s (PAM4) electrical signals. A DSP basis gearbox is used to convert 8 channels of 25GBaud PAM4 signals into 4 channels of 50GBaud PAM4 signals and also an 8-channel retimer and FEC block are integrated in this DSP. The electrical interface is compliant with IEEE 802.3bs and QSFP-DD MSA in the transmitting and receiving directions, and the optical interface is compliant to QSFP-DD MSA with MPO-12 connector.

A single +3.3V power supply is required to power up this product. All the power supply pins are internally connected and should be applied concurrently. As per MSA specifications the module offers seven low speed hardware control pins (including the 2-wire serial interface): ModSelL, SCL, SDA, ResetL, InitMode, ModPrsL and IntL.

Module Select (ModSelL) is an input pin. When held low by the host, this product responds to 2- wire serial communication commands. The ModSelL allows the use of this product on a single 2- wire interface bus – individual ModSelL lines must be used.

Serial Clock (SCL) and Serial Data (SDA) are required for the 2-wire serial bus communication interface and enable the host to access the memory map.

The ResetL pin enables a complete reset, returning the settings to their default state, when a low level on the ResetL pin is held for longer than the minimum pulse length. During the execution of a reset the host shall disregard all status bits until it indicates a completion of the reset interrupt. The product indicates this by posting an IntL (Interrupt) signal with the Data_Not_Ready bit negated in the memory map. Note that on power up (including hot insertion) the module should post this completion of reset interrupt without requiring a reset.

Initialize Mode (InitMode) is an input signal. It is pulled up to Vcc in the QSFP-DD module. The InitMode signal allows the host to define whether the QSFP-DD module will initialize under host software control (InitMode asserted High) or module hardware control (InitMode deasserted Low). Under host software control, the module shall remain in Low Power Mode until software enables the transition to High Power Mode, as defined in the QSFP-DD Management Interface Specification. Under hardware control (InitMode de-asserted Low), the module may immediately transition to High Power Mode after the management interface is initialized. The host shall not change the state of this signal while the module is present. In legacy QSFP applications, this signal is named LPMode. See SFF-8679 for LPMode signal description.

Module Present (ModPrsL) is a signal local to the host board which, in the absence of a product, is normally pulled up to the host Vcc. When the product is inserted into the connector, it completes the path to ground through a resistor on the host board and asserts the signal. ModPrsL then indicates its present by setting ModPrsL to a “Low” state.

Interrupt (IntL) is an output pin. “Low” indicates a possible operational fault or a status critical to the host system. The host identifies the source of the interrupt using the 2-wire serial interface. The IntL pin is an open collector output and must be pulled to the Host Vcc voltage on the Host board.

Transceiver Block Diagram

Figure 1. Transceiver Block Diagram

Pin Assignment and Description

The electrical pinout of the QSFP56-DD module is shown in Figure 2 below.

Figure 2. MSA Compliant Connector

Pin Definition

Recommended Power Supply Filter

Absolute Maximum Ratings

It has to be noted that the operation in excess of any individual absolute maximum ratings might cause permanent damage to this module.

Recommended Operating Conditions and Power Supply Requirements

Notes:

1. FEC provided by host system.

2. FEC required on host system to support maximum distance.

Electrical Characteristics

The following electrical characteristics are defined over the Recommended Operating Environment unless otherwise specified.

Notes:

1. With the exception to IEEE 802.3bs 120E.3.1.2 that the pattern is PRBS31Q or scrambled idle.

2. Meets BER specified in IEEE 802.3bs 120E.1.1.

3. DC common mode voltage generated by the host. Specification includes effectsof ground offset voltage.

Optical Characteristics

Notes:

1. Average launch power, each lane ( min) is informative and not the principal indicator of signal strength. A transmitter with launch power below this value cannot be compliant; however, a value above this does not ensure compliance.

   1. 2. Even if the TDECQ < 1.4dB for an extinction ratio of ≥ 4.5dB or TDECQ < 1.3dB for an extinction ratio of < 4 . 5 dB, the OMAouter ( min) must exceed the minimum value specified here.

2. Ceq is a coefficient defined in IEEE Std 802.3-2018 clause 121.8.5.3 which accounts for reference equalizer noise enhancement.

3. Average receive power, each lane ( min) is informative and not the principal indicator of signal strength. A received power below this value cannot be compliant; however, a value above this does not ensure compliance.

4. The receiver shall be able to tolerate, without damage, continuous exposure to a modulated optical input signal having this power level on one lane. The receiver does not have to operate correctly at this input power.

5. Receiver sensitivity ( OMAouter) is informative and is defined for a transmitter with a value of SECQ up to 3.4 dB. Receiver sensitivity should meet Equation ( 1 ) , which is illustrated in the figure below.

RS= max(-6.1, SECQ- 7.5) dBm (1)

Where: RS is the receiver sensitivity, and SECQ of the transmitter used to measure the receiver sensitivity.

1. Measured with conformance test signal at TP3 for the BER equal to 2.4x10-4.

2. These test conditions are for measuring stressed receiver sensitivity. They are not characteristics of the receiver.

Digital Diagnostic Functions

The following digital diagnostic characteristics are defined over the normal operating conditions unless otherwise specified.

Notes:

1. Due to measurement accuracy of different single mode fibers, there could be an additional +/-1 dB fluctuation, or a +/- 3 dB total accuracy.

Mechanical Dimensions

ESD

This transceiver is specified as ESD threshold 1kV for high speed data pins and 2kV for all other electrical input pins, tested per MIL-STD-883, Method 3015.4 /JESD22- A114-A (HBM). However, normal ESD precautions are still required during the handling of this module. This transceiver is shipped in ESD protective packaging. It should be removed from the packaging and handled only in an ESD protected environment.

Laser Safety

This is a Class 1 Laser Product according to EN 60825-1:2014. This product complies with 21 CFR 1040.10 and 1040.11 except for deviations pursuant to Laser Notice No. 50, dated (June 24, 2007).

Caution: Use of controls or adjustments or performance of procedures other than those specified herein may result in hazardous radiation exposure.

Licensing

The following U.S. patents are licensed by Finisar to FluxLight, Inc.:

U.S. Patent Nos: 7,184,668, 7,079,775, 6,957,021, 7,058,310, 6,952,531, 7,162,160, 7,050,720