Intel Compatible E40GQSFPER Quick Spec:

Part Number: E40GQSFPER E40GQSFPER-EXT E40GQSFPER-IND

Form Factor: QSFP

TX Wavelength: CWDM 1270nm-1330nm

Reach: 40km

Cable Type: SMF

Rate Category: 40GBase

Interface Type: ER4

DDM: Yes

Connector Type: Dual-LC

Optical Power Budget: 16.5dB

TX Power Min/Max: -3.70 to 4.50 dBm

RX Power Min/Max: -20.2 to -1.5 dBm

Intel Compatible E40GQSFPER Product Features

• Compliant with 40G Ethernet IEEE802.3ba and 40GBASE-ER4 Standard

• QSFP+ MSA compliant

• Compliant with QDR/DDR Infiniband data rates

• Up to 11.2Gb/s data rate per wavelength

• 4 CWDM lanes MUX/DEMUX design

• Up to 40km transmission on single mode fiber (SMF)

• Operating case temperature:

  • Standard 0 to 70oC

  • Extended -5 to +85 oC

  • Industrial -40 to +85 oC

• Maximum power consumption 3.5W

• LC duplex connector

• RoHS compliant

  
  

  Intel Compatible E40GQSFPER Applications

• 40GBASE-ER4 Ethernet Links

• Infiniband QDR and DDR interconnects

• Client-side 40G Telecom connections

Intel Compatible E40GQSFPER Overview

The E40GQSFPER is a transceiver module designed for 30km optical communication applications. The design is compliant to 40GBASE-ER4 of the IEEE P802.3ba standard. The module converts 4 inputs channels of 10 Gbps electrical data to 4 CWDM optical signals and multiplexes them into a single channel for 40 Gbps optical transmission. Reversely, on the receiver side, the module optically demultiplexes a 40Gbps input into 4 CWDM channels signals and converts them to 4 channel output electrical data. The central wavelengths of the 4 CWDM channels are 1271, 1291, 1311 and 1331 nm as members of the CWDM wavelength grid defined in ITU-T G694.2. It contains a duplex LC connector for the optical interface and a 148-pin connector for the electrical interface. To minimize the optical dispersion in the long-haul system, single-mode fiber (SMF) has to be used.

The product is designed with form factor, optical/electrical connection and digital diagnostic interface according to the QSFP+ Multi-Source Agreement (MSA). It has been designed to meet the harshest external operating conditions including temperature, humidity and EMI interference.

Intel Compatible E40GQSFPER Functional Diagram

This product converts the 4-channel 10 Gbps electrical input data into CWDM optical signals (light), by a driven 4- wavelength Distributed Feedback Laser (DFB) array. The light is combined by the MUX parts as a 40 Gbps data, propagating out of the transmitter module from the SMF. The receiver module accepts the 40 Gbps CWDM optical signals input, and de-multiplexes it into 4 individual 10Gbps channels with different wavelengths. Each wavelength is collected by a discrete avalanche photodiode (APD), and then outputted as electric data after amplified first by a TIA and then by a post amplifier. Figure 1 shows the functional block diagram of this product.

A single +3.3V power supply is required to power up this product. Both power supply pins VccTx and VccRx are internally connected and should be applied concurrently. As per MSA specifications the module offers 7 low speed hardware control pins (including the 2-wire serial interface): ModSelL, SCL, SDA, ResetL, LPMode, ModPrsL and IntL.

Module Select (ModSelL) is an input pin. When held low by the host, this product responds to 2-wire serial communication commands. The ModSelL allows the use of this product on a single 2-wire interface bus – individual ModSelL lines must be used.

Laser Driver Array (4ch)

DFB

Laser Array (4ch)

Micro- optics

LC duplex connector

Tx3 Tx2 Tx1 Tx0

Rx3 Rx2 Rx1 Rx0

Figure 1. Functional diagram

Serial Clock (SCL) and Serial Data (SDA) are required for the 2-wire serial bus communication interface and enable the host to access the QSFP+ memory map.

The ResetL pin enables a complete reset, returning the settings to their default state, when a low level on the ResetL pin is held for longer than the minimum pulse length. During the execution of a reset the host shall disregard all status bits until it indicates a completion of the reset interrupt. The product indicates this by posting an IntL (Interrupt) signal with the Data_Not_Ready bit negated in the memory map. Note that on power up (including hot insertion) the module should post this completion of reset interrupt without requiring a reset.

Low Power Mode (LPMode) pin is used to set the maximum power consumption for the product in order to protect hosts that are not capable of cooling higher power modules, should such modules be accidentally inserted.

Module Present (ModPrsL) is a signal local to the host board which, in the absence of a product, is normally pulled up to the host Vcc. When the product is inserted into the connector, it completes the path to ground though a resistor on the host board and asserts the signal. ModPrsL then indicates its present by setting ModPrsL to a “Low” state.

Interrupt (IntL) is an output pin. “Low” indicates a possible operational fault or a status critical to the host system. The host identifies the source of the interrupt using the 2-wire serial interface. The IntL pin is an open collector output and must be pulled to the Host Vcc voltage on the Host board.

Absolute Maximum Ratings

Recommended Operating Conditions

Recommended Power Supply Filter

Electrical Characteristics

Electrical Characteristics – Transmitter (each lane)

Electrical Characteristics – Receiver (each lane)

Notes:

1. Power-on initialization time is the time from when the power supply voltages reach and remain above the minimum recommended operating supply voltages to the time when the moduleis fully functional.

2. The single ended input voltage tolerance is the allowable range of the instantaneous input signals.

Optical Characteristics

Optical Characteristics - Transmitter

Note: Transmitter optical characteristics are measured with a single mode fiber.

Optical Characteristics - Receiver

Notes:

1. Even if the TDP < 0.8 dB, the OMA min must exceed theminimum value specified here.

2. The receiver shall be able to tolerate, without damage, continuous exposure to a modulated optical input signal having this power level on one lane. The receiver does not have to operate correctly at this input power.

3. Measured with conformance test signal at receiver inputfor BER = 1x10-12.

4. Vertical eye closure penalty and stressed eye jitter are test conditions for measuring stressed receiver sensitivity. They are not characteristics of the receiver.

   
   

   Digitial Diagnostics Function

   The following digital diagnostic characteristics are defined over the normal operating conditions unless otherwise specified.

   
   

   Parameter	Symbol	Min	Typ	Max	Unit	Notes
   Temperature monitor absolute error	DMITEMP	-3		3	deg. C	Over operating temperature range
   Supply voltage monitor absolute error	DMIVCC	-0.1		0.1	V	Over Full operating range
   Channel RX power monitor absolute error	DMIRX_CH	-2		2	dB	1
   Channel Bias current monitor	DMIIbias_CH	-10%		10%	mA
   Channel TX power monitor absolute error	DMITX_CH	-2		2	dB	1

   Note 1: Due to measurement accuracy of different multi-mode fibers, there could be an additional ±1dB fluctuation, or ± 3dB total accuracy.

   
   

   PIN Assignment and Function Definitions

   PIN Assignment

   
   

   

   
   

   PIN Definition

   PIN	Signal Name	Description
   1	GND	Ground (1)
   2	Tx2n	CML-I Transmitter 2 Inverted Data Input
   3	Tx2p	CML-I Transmitter 2 Non-Inverted Data Input
   4	GND	Ground (1)
   5	Tx4n	CML-I Transmitter 4 Inverted Data Input
   6	Tx4p	CML-I Transmitter 4 Non-Inverted Data Input
   7	GND	Ground (1)
   8	ModSelL	LVTLL-I Module Select
   9	ResetL	LVTLL-I Module Reset
   10	VCCRx	+3.3V Power Supply Receiver (2)
   11	SCL	LVCMOS-I/O 2-Wire Serial Interface Clock
   12	SDA	LVCMOS-I/O 2-Wire Serial Interface Data
   13	GND	Ground (1)
   14	Rx3p	CML-O Receiver 3 Non-Inverted Data Output
   15	Rx3n	CML-O Receiver 3 Inverted Data Output
   16	GND	Ground (1)
   17	Rx1p	CML-O Receiver 1 Non-Inverted Data Output
   18	Rx1n	CML-O Receiver 1 Inverted Data Output
   19	GND	Ground (1)
   20	GND	Ground (1)
   21	Rx2n	CML-O Receiver 2 Inverted Data Output
   22	Rx2p	CML-O Receiver 2 Non-Inverted Data Output
   23	GND	Ground (1)
   24	Rx4n	CML-O Receiver 4 Inverted Data Output
   25	Rx4p	CML-O Receiver 4 Non-Inverted Data Output
   26	GND	Ground (1)
   27	ModPrsL	Module Present
   28	IntL	Interrupt
   29	VCCTx	+3.3V Power Supply Transmitter (2)
   30	VCC1	+3.3V Power Supply
   31	LPMode	LVTLL-I Low Power Mode
   32	GND	Ground (1)
   33	Tx3p	CML-I Transmitter 3 Non-Inverted Data Input
   34	Tx3n	CML-I Transmitter 3 Inverted Data Input
   35	GND	Ground (1)
   36	Tx1p	CML-I Transmitter 1 Non-Inverted Data Input
   37	Tx1n	CML-I Transmitter 1 Inverted Data Input
   38	GND	Ground (1)

   Notes:

   1. All Ground (GND) are common within the QSFP+ module and all module voltages are referenced to this potential unless noted otherwise. Connect these directly to the host board signal common ground plane.

   2. VccRx, Vcc1 and VccTx are the receiving and transmission power suppliers and shall be applied concurrently. The connector pins are each rated for a maximum current of 500mA.

Licensing

The following U.S. patents are licensed by Finisar to FluxLight, Inc.:

U.S. Patent Nos: 7,184,668, 7,079,775, 6,957,021, 7,058,310, 6,952,531, 7,162,160, 7,050,720