3 QSFP-DD MSA

6 QSFP-DD/QSFP-DD800/QSFP112 Hardware Specification

8 for

10 QSFP DOUBLE DENSITY 8X AND QSFP 4X PLUGGABLE TRANSCEIVERS

13 Revision 6.3

16 July 26, 2022

Abstract: This specification defines: the electrical and optical connectors, electrical signals and power supplies,
mechanical and thermal requirements of the pluggable QSFP Double Density (QSFP-DD/QSFP-DD800) and
the QSFP112 module in the classic 4-lanes QSFP form factor, connector and cage system. This document
provides a common specification for systems manufacturers, system integrators, and suppliers of modules. 23

25 POINTS OF CONTACT:

Ali Ghiasi (Technical Editor) Ghiasi Quantum

19947 Lindenbrook Lane

Cupertino, CA 95014

ali at ghiasiquantum dot com

Mark Nowell (Co-Chair) Cisco

170 West Tasman Dr

San Jose, CA 95134 mnowell at cisco dot com

Scott Sommers (Co-Chair) Molex

2222 Wellington Court

Lisle, IL 60532-1682

scott.sommers at molex dot com

Website:
www.QSFP-DD.com

Limitation on use of Information:
This specification is provided "AS IS" with NO WARRANTIES whatsoever and therefore the provision of this
specification does not include any warranty of merchantability, noninfringement, fitness for a particular
purpose, or any other warranty otherwise arising out of any proposal, specification or sample. The authors
further disclaim all liability, including liability for infringement of any proprietary rights, relating to use of
information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted herein. 37

Permissions:
You are authorized to download, reproduce and distribute this document. All other rights are reserved. The
provision of this document should not be construed as the granting of any right to practice, make, use or
otherwise develop products that are based on the document. Any and all IP rights related to this document
and the designs disclosed within, except for the rights expressly mentioned above, are reserved by the
respective owners of those IP rights. 44

Dedication:
The members of the QSFP-DD MSA would like to acknowledge the contributions of Mr. Edmund Poh. He was

an excellent engineer; his technical skills and collaborative attitude will be missed. 4

5 The following are Promoter member companies of the QSFP-DD MSA.

Broadcom	Foxconn Interconnect Technology	Lumentum
Cisco	Huawei	Nvidia
Corning	Intel	Molex
II-VI	Juniper Networks	TE Connectivity

7 The following are contributing member companies of the QSFP-DD MSA.

ACON	H3C	Panduit
Alibaba Group	Hisense Broadband	PHY-SI
Amphenol	Hitachi Metals	Ranovus
Applied Optoelectronics	Hewlett Packard Enterprise	Samtec
Apresia	Infinera	Semtech
Celestica	InnoLight	Senko
Ciena	JPC	Sicoya
CIG	Keysight Technologies	The Siemon Company
ColorChip	Leoni	Skorpios
Credo	Lorom Cable Connection	Source Photonics
Dell Technologies	Luxshare ICT	Spectra7 Microsystems
Delta Products	Macom	Spirent
Dust Photonics	Marvell	Sumitomo Electric
Eoptolink	MaxLinear	US Conec
Fourte	MultiLane	Xilinx
Fujitsu Optical Components	NEC Corporation	Yamaichi
Genesis Connected Solutions	Nokia

2 Change History:

Revision	Date	Changes
1.0	Sept 19, 2016	First public release
2.0	March 13, 2017	Second public release
3.0	Sept 19, 2017	Third public release
4.0	Sept 18, 2018	Fourth public release, Additions of thermal chapter 10, synchronous clocking in 4.9, Mechanical updates.
5.0	July 9, 2019	Fifth public release, Added Module type 2A, changes to latch and cage drawings, added ePPS contact, updated power supply testing, added BiDi optical port assignments.
5.1	August 7, 2020	6th public release, Chapter 7-Management Interface is now part of Chapter 4. Port mapping, optical connectors, and module color coding moved into a new Chapter 6.
6.0	May 20, 2021	7th public release, chapters for QSFP-DD800 and QSFP112 Mechanical and Board Definitions are added. Chapter for QSFP112 Electrical and management timing added. Updated power supply test method. Module power contacts rating increased from 1 A to 1.5 A and max module power dissipation increased to at least 25 W. Programmable/Vendor specifics and ePPS/Clock contacts defined. Normative connector performance Appendix A added.
6.01	May 28, 2021	8th public release, reinstated text inadvertently deleted in PCB notes in section 7.3 and 8.3, inadvertent change to a dimension in Figure 55 corrected.
6.2	March 11, 2022	9th public release, defined a new improved power supply test method, squelch level reduced to 50 mV for 112G operation, press hole separation increased to 3.1 mm in Figure 78, corner radius added to Figure 88. TWI bus timing removed from chapter 4 as identical timing diagram already included in CMIS. QSFP112 specification has been forwarded to the SNIA TA TWG and chapter 5 and 9 are not being updated and will be removed when SNIA TA specification has been published.
6.3	July 26, 2022	10th public release, updated termination definition for P/VSx and ePPS/Clock signals, Figure 61 bezel opening height adjusted for consistency, updated Figure 85 glue zone, and updated Figure 95 to further clarify blocking features.

Foreword
The development work on this specification was done by the QSFP-DD MSA, an industry group. The
membership of the committee since its formation on Feb 2016 has included a mix of companies which are
leaders across the industry. 8

TABLE of CONTENTS
3

1 SCOPE 10
1.1 D ESCRIPTION OF C HAPTERS 10
2 REFERENCES AND ACRONYMS 11
2.1 R EFERENCE S TANDARDS AND S PECIFICATIONS 11
2.2 SFF S PECIFICATIONS 11
2.3 A CRONYMS AND ABBREVIATIONS 12
2.4 D OCUMENT S OURCE 12
3 INTRODUCTION 13
3.1 D OCUMENT O VERVIEW AND O RGANIZATION 13
3.2 A PPLICATIONS 14
3.3 M ODULE MANAGEMENT AND CONTROL 14
4 QSFP-DD/QSFP-DD800 ELECTRICAL SPECIFICATION AND MANAGEMENT INTERFACE TIMING 15
4.1 E LECTRICAL C ONNECTOR 15
4.2 L OW S PEED E LECTRICAL H ARDWARE S IGNALS 20
4.2.1 ModSelL 20
4.2.2 ResetL 20
4.2.3 LPMode/TxDis 20
4.2.4 ModPrsL 21
4.2.5 IntL/RxLOSL 21
4.2.6 Programmable/Vendor Specific (Optional) 21
4.2.7 ePPS/Clock PTP Reference Clock (Optional) 21
4.3 E XAMPLES OF QSFP-DD/QSFP-DD800 H OST B OARD S CHEMATIC 23
4.4 L OW S PEED E LECTRICAL S PECIFICATION 27
4.4.1 TWI Logic Levels and Bus Loading 27
4.5 M ANAGEMENT I NTERFACE 28
4.5.1 Management Interface Timing Specification 29
4.5.2 Timing for soft control and status functions 31
4.6 H IGH S PEED E LECTRICAL S PECIFICATION 34

32 4.6.1 Rx(n)(p/n) 34

33 4.6.2 Tx(n)(p/n) 34

4.7 P OWER R EQUIREMENTS 35
4.7.1 Power Classes and Maximum Power Consumption 35
4.7.2 Host Board Power Supply Filtering 36
4.7.3 Module Power Supply Specification 36
4.7.4 Host Board Power Supply Noise Output 38
4.7.5 Module Power Supply Noise Output 39
4.7.6 Module Power Supply Noise Tolerance 40

41 4.8 ESD 42

11 5.6.1 Rx(n)(p/n) 60

12 5.6.2 Tx(n)(p/n) 60

5.7 P OWER R EQUIREMENTS 61
5.7.1 QSFP112 Power Classes and Maximum Power Consumption 61
5.7.2 QSFP112 Host Board Power Supply Filtering 62
5.7.3 Module Power Supply Specification 62
5.7.4 Host Board Power Supply Noise Output 64
5.7.5 Module Power Supply Noise Output 65
5.7.6 Module Power Supply Noise Tolerance 66

20 5.8 ESD 66

5.9 C LOCKING C ONSIDERATIONS 67
5.9.1 Data Path Description 67
5.9.2 TX Clocking Considerations 67
5.9.3 Rx Clocking Considerations 67
6 OPTICAL PORT MAPPING AND OPTICAL INTERFACES 68
6.1 E LECTRICAL DATA INPUT /OUTPUT TO OPTICAL PORT MAPPING 68
6.2 O PTICAL I NTERFACES 68
6.2.1 MPO Optical Cable connections 71
6.2.2 Duplex LC Optical Cable connection 74
6.2.3 Dual CS Optical Cable connection 74
6.2.4 Quad SN Optical Cable connections 75
6.2.5 Quad MDC Optical Cable connection 75
6.2.6 Dual SN Optical Cable connections 76
6.2.7 Dual MDC Optical Cable connection 76
6.2.8 Dual Duplex LC Optical Cable connection 77
6.2.9 Dual MPO-12 Optical Cable connection 78
6.3 M ODULE C OLOR C ODING AND L ABELING 79
7 QSFP-DD MECHANICAL AND BOARD DEFINITION 80
7.1 I NTRODUCTION TO QSFP-DD/QSFP-DD800 M ODULES 80
7.2 D ATUMS , D IMENSIONS AND C OMPONENT A LIGNMENT 82
7.3 M ODULE F ORM F ACTORS FOR QSFP-DD/QSFP-DD800 84
7.4 M ODULE F LATNESS AND R OUGHNESS 92
7.5 QSFP-DD MODULE PADDLE CARD DIMENSIONS NOTES 93
7.6 M ODULE E XTRACTION AND R ETENTION F ORCES 95
7.7 QSFP-DD 2 X 1 S TACKED E LECTRICAL C ONNECTOR M ECHANICAL 95
7.7.1 QSFP-DD 2x1 Connector and Cage host PCB layout 100
7.8 QSFP-DD S URFACE M OUNT E LECTRICAL C ONNECTOR M ECHANICAL 103
7.8.1 QSFP-DD Surface mount connector and cage host PCB layout 109
8 QSFP-DD800 MECHANICAL AND BOARD DEFINITION 111
8.1 I NTRODUCTION 111
8.2 QSFP-DD800 MODULE MECHANICAL DIMENSIONS 111
8.3 QSFP-DD800 IMPROVED MODULE PADDLE CARD DIMENSIONS 116

8.4 QSFP-DD800 1 X 1 SMT CONNECTOR /CAGE 119
8.4.1 Surface mount connector and cage host PCB layout 119
8.5 2 X 1 S URFACE M OUNT T ECHNOLOGY (SMT) C ONNECTOR /C AGE 120
8.5.1 2x1 SMT Connector/Cage System 120
8.5.2 2x1 SMT Connector and Cage host PCB layout 125
9 QSFP112 MECHANICAL AND BOARD DEFINITION 129
9.1 I NTRODUCTION 129
9.2 QSFP112 MODULE MECHANICAL DIMENSIONS 129
9.3 QSFP112 IMPROVED MODULE PADDLE CARD DIMENSIONS 129
9.4 QSFP112 1 X 1 SURFACE MOUNT CONNECTOR /CAGE 130
9.4.1 QSFP112 SMT host PCB layout 133
9.5 QSFP112 2 X 1 S TACKED S URFACE M OUNT C ONNECTOR /C AGE 136
9.5.1 QSFP112 2x1 SMT host PCB layout 141
10 MODULE ENVIRONMENTAL AND THERMAL REQUIREMENTS 144
10.1 T HERMAL R EQUIREMENTS 144
10.2 T HERMAL R EQUIREMENTS – TIGHTER CONTROLLED ENVIRONMENTS 144
10.3 E XTERNAL C ASE AND H ANDLE T OUCH T EMPERATURE 144
APPENDIX A NORMATIVE MODULE AND CONNECTOR PERFORMANCE REQUIREMENTS 145
A.1 QSFP-DD/QSFP-DD800 P ERFORMANCE T ABLES 145
A.2 T EST 145
APPENDIX B INFORMATIVE OVERALL MODULE LENGTH WITH ELASTOMERIC HANDLE 149
APPENDIX C INFORMATIVE QSFP-DD/QSFP-DD800 MODULE HEAT SINK TYPE 2A AND 2B EXAMPLES 150
APPENDIX D QSFP-DD800 CAGE AND HEAT SINK MECHANISM AND EMI FINGERS 157
D.1 I NTRODUCTION 157
D.2 M ECHANICAL D EFINITION 157
D.3 EMI S PRING C LIP 157
D.4 H EAT S INK A TTACH M ECHANISM 158
D.5 H OST PCB L AYOUT 158
D.6 F RONT P ANEL C UTOUT 158
APPENDIX E INFORMATIVE QSFP-DD800 2X1 CABLED CONNECTOR AND CAGE 159
E.1 2 X 1 C ABLED U PPER C ONNECTOR /C AGE 159
E.2 2 X 1 CABLED CONNECTOR /CAGE E LECTRICAL C ONNECTOR M ECHANICAL 160
E.3 2 X 1 C ABLED C ONNECTOR AND C AGE HOST PCB LAYOUT 166

1 List of Tables

Table 1- Pad Function Definition 18
Table 2- ePPS/Clock Advertising Capabilities 22
Table 3- ePPS or Clock Modes 22
Table 4- ePPS or Clock Frequency 22
Table 5- Module ePPS/Clock Status Reporting (Required if module supports ePPS/Clock) 23
Table 6- ePPS RF or Clock Frequency Reporting (Optional) 23
Table 7- Low Speed Control and Sense Signals 27
Table 8- Management Interface timing parameters 30
Table 9- Timing for QSFP-DD soft control and status functions 31
Table 10- I/O Timing for Squelch & Disable 33
Table 11- TX Squelch Levels 34
Table 12- Power Classes 35
Table 13- Power supply specifications, instantaneous, sustained, and steady state current limits 37
Table 14- Power Supply Output Noise and Tolerance Specifications 40
Table 15- QSFP112 Pad Function Definition 45
Table 16- Low Speed Control and Sense Signals 51
Table 17- Management Interface timing parameters 54
Table 18- Timing for QSFP112 soft control and status functions 58
Table 19- I/O Timing for Squelch & Disable 59
Table 20- QSFP112 Power Classes 61
Table 21- Power supply specifications, instantaneous, sustained, and steady state current limits 63
Table 22- Truncated Filter Response Coefficients for Host Power Supply Noise Output 65
Table 23- Power Supply Output Noise and Tolerance Specifications 66
Table 24- Electrical Signal to Optical Port Mapping 68
Table 25- Datums 82
Table 26- QSFP-DD/QSFP-DD800 Module flatness specifications 92
Table 27- QSFP112 Module flatness specifications 92
Table 28- Optional Enhanced Module flatness specifications 92
Table 29- Temperature Range Class of operation 144
Table 30- Temperature Range Classes for Tighter Controlled Applications 144
Table 31- Form Factor Performance Requirements 146
Table 32- EIA-364-1000 Test Details 147
Table 33- Additional Test Procedures 148
Table 34- Dimensions for QSFP-DD/QSFP-DD800 and Module Type 2A/2B 150

38 List of Figures

Figure 1: Application Reference Model 14
Figure 2: Module pad assignment and layout 17
Figure 3: Example QSFP-DD/QSFP-DD800 host board schematic for Optical Modules 24
Figure 4: Example QSFP-DD/QSFP-DD800 host board schematic for Active Copper Cables Module 25
Figure 5: Example QSFP-DD/QSFP-DD800 host board schematic of Passive Copper Cables Module 26
Figure 6: SDA/SCL options for pull-up resistor, bus capacitance and rise/fall times 28
Figure 7: TWI Timing Diagram 29
Figure 8: Reference Power Supply Filter for Module Testing 36
Figure 9: Instantaneous and sustained peak currents for Icc Host (see Table 13) 38
Figure 10: Host Noise Output Measuremnt 39
Figure 11: Module Noise Output Measuremnt 39
Figure 12: Module High Frequency Noise Tolerance 41
Figure 13: Module Low Frequency Noise Tolerance 41
Figure 14: QSFP112 module pad assignment and layout 44
Figure 15: Example QSFP112 Host Board Schematic for Optical Modules 48

Figure 16: Example QSFP112 host board schematic for Active Copper Cable Module 49
Figure 17: Example QSFP112 Host Board Schematic for Passive Copper Cable Module 50
Figure 18: SDA/SCL options for pull-up resistor, bus capacitance and rise/fall times 52
Figure 19: TWI Timing Diagram 53
Figure 20: Bus timing tWR 55
Figure 21: Bus timing tNACK 56
Figure 22: Bus timing tBPC 57
Figure 23: Reference Power Supply Filter for Module Testing 62
Figure 24: Instantaneous and sustained peak currents for Icc Host (see Table 13) 64
Figure 25: Truncated Transfer Response for Host Board Power Supply Noise Output measurement 65
Figure 26: Module Noise Injection Point 66
Figure 27: Optical Media Dependent Interface port assignments 70
Figure 28: MPO-12 One row optical patchcord and module receptacle 71
Figure 29: MPO-16 One row optical patchcord and module receptacle 72
Figure 30: MPO-12 Two row optical patchcord and module receptacle 73
Figure 31: Duplex LC optical patchcord and module receptacle 74
Figure 32: Dual CS connector optical patchcord and module receptacle 74
Figure 33: Quad SN optical connector pathcord and four-port module receptacle 75
Figure 34: Quad MDC optical connector patchcord and four-port module receptacle 75
Figure 35: Dual SN optical connector patchcord and dual-port module receptacle 76
Figure 36: Dual MDC optical connector patchcord and dual-port module receptacle 76
Figure 37: Dual Duplex LC module receptacle (in support of breakout applications) 77
Figure 38: Dual Duplex LC module receptacle port pitch 77
Figure 39: Dual Duplex LC latch width 77
Figure 40: Dual MPO module receptacle (in support of breakout applications) 78
Figure 41: Dual MPO-12 module receptacle port pitch 78
Figure 42: 2x1 stacked cage and module 80
Figure 43: Press fit cage for surface mount connector 81
Figure 44: Type 1, Type 2, Type 2A, and Type 2B pluggable modules 81
Figure 45: 2X1 stacked press fit connector/cage datum descriptions 83
Figure 46: Surface mount connector/cage datum descriptions 84
Figure 47: Type 1 module 85
Figure 48: Type 2 module 85
Figure 49: Type 2A Module 86
Figure 50: Type 2B module 86
Figure 51: Type 2A Module with heat sink 88
Figure 52: Drawing of the QSFP-DD module 89
Figure 53: Drawing of QSFP-DD module end face 90
Figure 54: Detailed dimensions of the QSFP-DD module opening 91
Figure 55: Module paddle card dimensions 94
Figure 56: Detail module pad dimensions 95
Figure 57: Integrated connector in the 2x1 stacked cage 96
Figure 58: 2x1 stacked cage 97
Figure 59: 2x1 stacked cage dimensions 98
Figure 60: Connector pads in 2x1 stacked cage as viewed from front 99
Figure 61: 2x1 Bezel Opening 99
Figure 62: 2X1 host board connector contacts 100
Figure 63: 2X1 Host PCB layout 101
Figure 64: 2X1 Host PCB detail layout 102
Figure 65: SMT connector in 1xn cage 103
Figure 66: SMT 1x1 cage overview 104
Figure 67: SMT 1x1 cage detail design 105
Figure 68: SMT 1x1 connector front and side views 106

Figure 69: SMT 1x1 connector detail design 107
Figure 70: SMT 1x1 bezel opening 108
Figure 71: SMT host PCB layout 109
Figure 72: SMT Connector and host PCB contact numbers 110
Figure 73: QSFP-DD800 module dimensions 113
Figure 74: QSFP-DD800 module leading edge dimensions 114
Figure 75: Detailed dimensions of the module opening 115
Figure 76: QSFP-DD800 Module paddle card dimensions 117
Figure 77: QSFP-DD800 detail module paddle card dimensions 118
Figure 78: Reduced pad SMT host PCB layout 119
Figure 79: QSFP-DD800 2x1 SMT Stack Cage 121
Figure 80: QSFP-DD800 2x1 SMT cage dimensions 122
Figure 81: Connector pads in 2x1 SMT stacked cage as viewed from front 123
Figure 82: 2x1 SMT Bezel Opening 123
Figure 83: 2x1 SMT Pads Labeling 124
Figure 84: QSFP-DD800 stacked SMT 2x1 connector 125
Figure 85: 2x1 SMT Connector and Cage PCB Layout Implementation 1 126
Figure 86: 2x1 SMT Connector and Cage PCB Layout Implementation 2 127
Figure 87: Detail QSFP800 2x1 SMT connector host layout 128
Figure 88: QSFP112 improved paddle card dimensions 130
Figure 89: QSFP112 SMT 1x1 cage overview 131
Figure 90: QSFP112 SMT 1x1 cage detail design 132
Figure 91: QSFP112 SMT 1x1 connector front and side views 133
Figure 92: 1x1 SMT connector PCB layout implementation 134
Figure 93: Alternate QSFP112 1x1 SMT connector PCB layout with QSFP28 Style A Cage 135
Figure 94: QSFP112 2x1 SMT Connector and Cage System 137
Figure 95: QSFP112 2x1 SMT Connector and Cage Detail View 138
Figure 96: QSFP112 2x1 stacked SMT connector 139
Figure 97: Connector pads in 2x1 SMT stacked cage as viewed from front 140
Figure 98: 2x1 SMT Bezel Opening 140
Figure 99: 2x1 SMT host pads labeling 141
Figure 100: QSFP112 2x1 SMT connector host layout implementation 1 142
Figure 101: QSFP112 2x1 SMT connector host layout implementation 2 143
Figure 102: Informative overall module length with handle for Type 1 module 149
Figure 103: Informative overall module length with handle for Type 2A and Type 2B modules 149
Figure 104: Example of single and dual stacked QSFP-DD/QSFP-DD800 module insertions 151
Figure 105: Type 2A and 2B example of 1X1 bezel design 152
Figure 106: Type 2A and 2B example of 2X1 bezel design 153
Figure 107: Example of extruded Heat Sink 154
Figure 108: Example of die Cast Heat Sink with Metal Cover 155
Figure 109: Example of zipper Fin Heat Sink 156
Figure 110: Dual grounding path for EMI spring clip 157
Figure 111: EMI spring clip 157
Figure 112: Cage with integrated heat sink clips and EMI latch shield 158
Figure 113: 1xn cage (side view) 158
Figure 114: 2x1 Cabled upper connector/cage 159
Figure 115: 2x1 Cabled upper connector/cage illustration 160
Figure 116: Cabled upper connector over existing surface mount connector 161
Figure 117: Lower SMT connector, upper press fit connector, and the 2x1 cage 162
Figure 118: 2x1 Cabled over SMT connector and cage - Top View 163
Figure 119: 2x1 Cabled over SMT connector and cage – Side View 164
Figure 120: Cabled upper connector and surface mount connector dimensions 165

54 Figure 121: 2x1 Cabled upper connector/cage host board connector contacts 167

1 Scope ‌
The scope of this specification is the definition of high-speed/density 4 and 8 electrical lanes (4x, 8x) modules,
cage and connector system. The QSFP-DD and QSFP112 both supports up to 400 Gb/s in aggregate
respectively over 8 lanes of 50 Gb/s and over 4 lanes of 100 Gb/s electrical interfaces. The QSFP-DD800
supports up to 800 Gb/s in aggregate over 8 lanes of 100 Gb/s electrical interface. The QSFP-DD/QSFP-
DD800 cage and connector designs with 8 lanes are compatible with the 4 lanes QSFP28/QSFP112. The
QSFP-DD800 cage and connector is an incremental design with enhanced signal integrity and thermal which is
backwards compatible to 8 lanes QSFP-DD and 4 lanes QSFP28. The QSFP112 cage and connector is an
incremental design with enhanced signal integrity and thermal which is backwards compatible to 4 lanes
QSFP28/QSFP+. The QSFP-DD800/QSFP112 supports up to 112 Gb/s (56 GBd) per lane electrical operation
based on PAM4 signaling and is expected to be compliant to IEEE 802.3ck [17] and OIF 112G-VSR [22] when
published.

This specification is intended to be used in combination with the Common Management Interface Specification
(CMIS) [5]. Mutual dependencies exist between these two documents for timing parameters, management
interface and register specifications.
1.1 Description of Chapters ‌
QSFP-DD/QSFP-DD800/QSFP112 specifications are organized in to 10 chapters and 5 appendixes
addressing electrical/management, optical, mechanical, and environmental aspect of the module. 20

21 All the requirements shall be considered for both QSFP-DD and QSFP-DD800 unless otherwise specified, 7.1,

22 7.2, 7.3, 7.4 are mechanical foundation sections applicable to QSFP-DD/QSFP-DD800 and QSFP112.

23 QSFP112 requirements are organized into chapters 1, 2, 3, 5, and 9.

25  Chapter 1 Scope and Purpose

27  Chapter 2 References, Related Standards, and SFF Specifications

29  Chapter 3 Introduction

31  Chapter 4 QSFP-DD/QSFP-DD800 Electrical Specifications and Management Interface Timing 32

33  Chapter 5 QSFP112 Electrical Specifications and Management Interface Timing

35  Chapter 6 Optical Port Mapping and Optical Interfaces 36

37  Chapter 7 Mechanical specifications and printed circuit board definition for QSFP-DD

39  Chapter 8 Mechanical specifications and printed circuit board definition for QSFP-DD800 40

41  Chapter 9 Mechanical specifications and printed circuit board definition for QSFP112

43  Chapter 10 Environmental and thermal considerations. 44

45  Appendix A Normative Module and Connector performance requirements 46

47  Appendix B Informative overall module length with elastomeric handle

49  Appendix C Informative QSFP-DD/QSFP-DD800 Module Type 2A and 2B Heat Sink Examples 50

51  Appendix D QSFP-DD800 Cage and Heat Sink Mechanism and EMI fingers

53  Appendix E Informative QSFP-DD800 2x1 Cabled Connector and Cage.

1	2 ‌	References and Acronyms
2	2.1 ‌	Reference Standards and Specifications
3	The	following documents are relevant to this specification:
4	[1]	ANSI FC-PI-6 32GFC
5	[2]	ANSI FC-PI-7 64GFC
6	[3]	ANSI FC-PI-8 128GFC
7	[4]	ASME Y14.5-2009 Dimensioning and Tolerancing
8	[5]	Common Management Interface Specification (CMIS) 5.2,
9		see https://www.oiforum.com/wp-content/uploads/OIF-CMIS-05.2.pdf
10	[6]	CS-01242017 CS optical connector and receptacle, see http://www.qsfp-dd.com/optical-connector/
11	[7]	EIA-364-1000 TS-1000B Environmental Test Methodology for Assessing the Performance of Electrical
12		Connectors and Sockets Used in Controlled Environment Applications, revision B 2009
13	[8]	EN6100-4-2 (IEC immunity standard on ESD), criterion B test specification
14	[9]	Human Body Model per ANSI/ESDA/JEDEC JS-001
15	[10]	IEC/UL 60950-1 Requirements for Information Technology Equipment, Section 4.5.4 (Touch Temperature
16		Reference)
17	[11]	IEC 61754-7-1 (Fibre Optic Interconnecting Devices and Passive Components - Fibre Optic Connector
18		Interfaces - Part 7-1: Type MPO Connector Family - One Fibre Row)
19	[12]	IEC 61754-7-2 (Fibre Optic Interconnecting Devices and Passive Components - Fibre Optic Connector
20		Interfaces - Part 7-2: Type MPO Connector Family - Two Fibre Rows)
21	[13]	IEC 61754-7-3 (Fibre Optic Interconnecting Devices and Passive Components - Fibre Optic Connector
22		Interfaces - Part 7-3: Type MPO Connector Family - Two Fibre Rows 16 Fibre Wide)
23	[14]	IEC 61754-20 (Fibre Optic Interconnecting Devices and Passive Components - Fibre Optic Connector
24		Interfaces - Part 20: Type LC Connector Family)
25	[15]	IEEE Std 802.3TM-2018
26	[16]	IEEE Std 802.3cd (50 Gb/s, 100 Gb/s, and 200 Gb/s Ethernet)
27	[17]	IEEE Std 802.3ck (100 Gb/s, 200 Gb/s, and 400 Gb/s Electrical Interfaces)
28	[18]	IEEE Std 1588 Precision Clock Synchronization Protocol PTP, 2019
29	[19]	InfiniBand Architecture Specification Volume 2
30	[20]	JEDEC JESD8C.01 Interface Standard for Nominal 3.0/3.3 V Supply Digital Integrated Circuit (LVCMOS)
31	[21]	NXP UM10204, I2C-bus specification and user manual, Rev 6 – 4 April 2014.
32	[22]	OIF CEI 5.0, CL-13 CEI-28G-VSR, CL-16 CEI-56G-VSR PAM4, and CEI-112G-VSR PAM4 specifications
33	[23]	SN-60092019 SN optical connector and receptacle, see http://www.qsfp-dd.com/optical-connector/
34	[24]	Telcordia GR63 NEBSTM Requirements: Physical Protection, Section 4.1.7, December 2017
35	[25]	TIA-604-5 (FOCIS 5 Fiber Optic Connector Intermateability Standard- Type MPO)
36	[26]	TIA-604-10 (FOCIS 10 Fiber Optic Connector Intermateability Standard- Type LC)
37	[27]	TIA-604-18 (FOCIS 18 Fiber Optic Connector Intermateability Standard- Type MPO-16) Interfaces - Part 7-
38		1: Type MPO Connector Family - One Fibre Row)
39	[28]	USC-11383001 MDC optical plug and receptacle, see http://www.qsfp-dd.com/optical-connector/
40	2.2	SFF Specifications:
41	[29]	SFF-8431 SFP+ 10 Gb/s and Low Speed Electrical Interface, Rev. 4.1
42	[30]	SFF-8636 Management Interface for Cabled Environments, Rev. 2.10a
43	[31]	SFF-8661 Specification for QSFP+ 4X Module, Rev. 2.5
44	[32]	SFF-8679 QSFP28 4X Base Electrical Specifications, Rev. 1.8.

2.3 Acronyms and abbreviations ‌
The following acronyms may be used in this specification.
ASIC - Application Specific Integrated Circuit
CDR - Clock and Data Recovery
CMIS – Common Management Interface Specifications
DCR – DC Resistance
DSP – Digital Signal Processing
EMI - Electromagnetic Interference
ESD - Electrostatic Discharge
ESR - Equivalent Series Resistance
Gb/s - Gigabits per second
GBd – Gigabaud
HCB - Host Compliance Board
IntL – Interrupt on Low Transition
I/O – Input/Output
LOS – Loss of Signal
LVCMOS - Low Voltage Complementary Metal Oxide Semiconductor
LVTTL - Low Voltage Transistor-Transistor Logic
MCB - Module Compliance Board
NEBS - Network Equipment Building System
OMA - Optical Modulation Amplitude
PAM – Pulse Amplitude Modulation
PCB - Printed Circuit Board
PPS – Pulse Per Seconds
PSU – Power Supply Unit
PSNR – Power Supply Noise Rejection
PTP – Precision Time Protocol
Rx – Receive Lanes
Retimer – A device that uses a recovered clock to retime the data also referred to as a CDR
SerDes - Serializer-Deserializer
SMT – Surface Mount Technology
TIA – Transimpedance Amplifier
TTL – Transistor-Transistor Logic
Tx – Transmit Lanes
TWI – Two wire interface compatible with NXP I2C [21].‌
2.4 Document Source
The QSFP-DD/QSFP-DD800/QSFP112 Hardware Specification for QSFP DOUBLE DENSITY 8X AND QSFP
4X PLUGGABLE TRANSCEIVER can be obtained via the www.QSFP-DD.com web site. 39

3 Introduction ‌
This Specification covers the following items:

a) Electrical interfaces including pad assignments for data, control, status and power supplies and host
PCB layout requirements. 7

b) Optical interfaces (including optical receptacles and mating fiber plugs for multimode and single-mode
duplex and parallel fiber applications). Breakout cable applications are also specified. Optical signaling
specifications are not included in this document but are defined in the applicable industry standards.
11
12 c) Mechanical specifications including dimensions and tolerances for the connector, cage and module
13 system. Includes details of the requirements for correct mating of the module and host sides of the
14 connector.
15
16 d) Thermal requirements
17
18 e) Electrostatic discharge (ESD) requirements by reference to industry standard limits and test methods. 19
20 f) Timing requirements for management interface, low speed I/O, soft control and status functions.
21
22 This Specification does not cover the following items:
23
1. a) Electromagnetic interference (EMI) protection. EMI protection is the responsibility of the implementers
2. of the cages and modules. 26
1. b) Memory map definition, which can be found in the 'Common Management Interface Specification for
2. 8x/16x pluggable transceivers' (see www.QSFP-DD.com ). 29
1. 3.1 Document Overview and Organization ‌
2. Implementations compliant to electrical signal contact and lane assignments, electrical and power
3. requirements for QSFP-DD/QSFP-DD800 are defined in Chapter 4 and the requirements for QSFP112 are
4. defined in Chapter 5. The optical lane assignments are defined in Chapter 6 ensure that the pluggable
5. modules and cable assemblies are functionally interchangeable. Dimensions, mounting and insertion
6. requirements defined in Chapter 7 for the bezel, optical module, cable plug, cage and connector system on a
7. circuit board ensure that these products are mechanically interchangeable. Chapter 8 describes an improved
8. QSFP-DD form factor called QSFP-DD800 with improved signal integrity for 100 Gb/s per lane operation with
9. an aggregate bandwidth of 800 Gb/s. Chapter 9 describes an improved QSFP+ form factor called QSFP112
10. with improved signal integrity for 100 Gb/s per lane operation and with an aggregate bandwidth of 400 Gb/s.
11. Environmental and thermal considerations are defined in Chapter 10. 41
1. Normative connector performance tables are in Appendix A, informative module overall length in Appendix B,
2. informative QSFP-DD/QSFP-DD800 module type 2A/2B heat sink examples in Appendix C, informative QSFP-
3. DD800 cage, heat sink, and EMI fingers in Appendix D, informative QSFP-DD800 2x1 cabled connector and
4. cage system in Appendix E. 46
47
48
49
1. 3.2 Applications ‌
2. This specification defines a common eight-lanes and four-lanes pluggable modules (including cables) which
4 may satisfy e.g., Ethernet, InfiniBand, and/or Fibre Channel requirements. The QSFP-DD/QSFP-
1. DD800/QSFP112 specifications are applicable to pluggable modules or direct attach cables based on
2. multimode fiber, single mode fiber or copper wires. QSFP-DD/QSFP-DD800/QSFP112 application reference
3. model is shown in Figure 1, where the focus of this specification is mechanical, electrical and thermal behavior
4. at the interface between a host and the QSFP-DD/QSFP-DD800/QSFP112 modules. 9
10
Figure 1: Application Reference Model

Note: For high speed electrical signals and compliance board methodology for 50 Gb/s/lane C2M operation
see IEEE 802.3 CL 120E [15] and OIF CEI-56G-VSR-PAM4 (CEI 4.0 CL 16) [22], and for copper cabling see
IEEE 802.3cd CL 136 [16]. For high speed electrical signals and compliance board methodology for 100
Gb/s/lane C2M operation see IEEE 802.3ck CL 120G and OIF CEI-112G-VSR drafts, and for copper cabling
see IEEE 802.3ck CL 162 draft. 19

3.3 Module management and control ‌
The CMIS memory management map is defined for QSFP-DD, QSFP-DD800, and QSFP112 module
management and control. Note: The CMIS management memory map structurally supports multiples of 8
lanes. In case of QSFP112 plugged into QSFP-DD/QSFP-DD800 or into QSFP112 socket, host lanes 5-8 are
physically not connected and should be ignored. The QSFP112 make use of host lanes 1-4 only. 25

4 QSFP-DD/QSFP-DD800 Electrical Specification and Management Interface Timing ‌
This Chapter contains signal definitions and requirements that are specific to the QSFP-DD/QSFP-DD800
modules. High-speed signal requirements including compliance points for electrical measurements are defined
in the applicable industry standard. 5

This Chapter contains signal definitions and requirements that are specific to the QSFP-DD/QSFP-DD800
hosts and modules. Hosts designed to the requirements of this chapter accept modules in the QSFP family as
well as QSFP-DD/QSFP-DD800 modules. Requirements for QSFP112 hosts and modules are provided in 5.
High-speed signal requirements including compliance points for electrical measurements are defined in the

applicable industry standards. 11

4.1 Electrical Connector ‌
The QSFP-DD/QSFP-DD800 module edge connector consists of a single paddle card with 38 pads on the top
and 38 pads on the bottom of the paddle card for a total of 76 pads. The pads are defined in such a manner to
accommodate insertion of a classic QSFP+/QSFP28/QSFP112 module into a QSFP-DD/QSFP-DD800
receptacles. The classic QSFP+/QSFP28/QSFP112 signal locations are deeper on the paddlecard, so that
classic QSFP+/QSFP28/QSFP112 module pads only connect to the longer row of connector pads, leaving the
short row of connector pads unconnected in a QSFP+/QSFP28/QSFP112 applications. 19

20 The pads are designed for a sequenced mating:

First mate “1A/1B”– ground pads
Second mate “2A/2B”– power pads
Third mate “3A/3B”– signal pads 25

Where color green identifies ground pads, color red identifies power pads, color orange identifies low speed
signal/control pads, and color blue identifies high speed I/O pads. 28

Because the QSFP-DD/QSFP-DD800 modules have 2 rows of pads, the additional QSFP-DD/QSFP-DD800
pads will have an intermittent connection with the classic QSFP+/QSFP28/QSFP112 pads in the connector
during the module insertion and removal. The 'classic' QSFP+/QSFP28/QSFP112 pads have a 'B' label shown
in Table 1 to designate them as the second row of module pads to contact the QSFP-DD/QSFP-DD800
connectors. The additional QSFP-DD/QSFP-DD800 pads have an 'A' label in Table 1 to designate them as
the first row of module pads to contact the QSFP-DD/QSFP-DD800 connectors. 35

The additional QSFP-DD/QSFP-DD800 pads have first, second and third mate to the connector pads for both
insertion and removal. Each of the first, second and third mate connections of the classic
QSFP+/QSFP28/QSFP112 pads and the respective additional QSFP-DD/QSFP-DD800 pads are
simultaneous.

Figure 2 shows the signal symbols and pad numbering for the QSFP-DD/QSFP-DD800 module edge
connectors. The diagram shows the module PCB edge as a top and bottom view. There are 76 pads intended
for high speed signals, low speed signals, power and ground connections. 44

Table 1 provides more information about each of the 76 pads. Figure 55 and Figure 56 show QSFP-DD pad
dimensions and Figure 76 and Figure 77 show QSFP-DD800 pad dimensions. The QSFP-DD connector can
be integrated into a 2x1 stacked configuration with 2 ports as illustrated in Figure 57 Figure 43or a surface
mount configuration as shown in Figure 46. The QSFP-DD800 connector can be integrated into a 2x1 stacked
SMT configuration with 2 ports as illustrated in Figure 79, Figure 43 a surface mount configuration which is
identical to QSFP-DD 1x1 SMT as shown in Figure 46, and a 2x1 cabled connector cage system as shown by
Figure 116.

For EMI protection the signals from the host connector should be shut off when the QSFP-DD/QSFP-DD800
modules are not present. Standard board layout practices such as connections to Vcc and GND with vias, use
of short and equal-length differential signal lines are recommended. The chassis ground (case common) of the
QSFP-DD/QSFP-DD800 modules should be isolated from the module’s circuit ground, GND, to provide the
equipment designer flexibility regarding connections between external electromagnetic interference shields and
circuit ground, GND, of the module.

38 GND

37 TX1n

36 TX1p

35 GND

34 TX3n

33 TX3p

32 GND

31 LPMode/TxDis

30 Vcc1

29 VccTx

28 IntL/RxLOS

27 ModPrsL

26 GND

25 RX4p

24 RX4n

23 GND

22 RX2p

21 RX2n

20 GND

76 GND

75 TX5n

74 TX5p

73 GND

72 TX7n

71 TX7p

70 GND

69 ePPS/Clock

68 Vcc2

67 VccTx1

66 Reserved

65 NC

64 GND

63 RX8p

62 RX8n

61 GND

60 RX6p

59 RX6n

58 GND

Module Card Edge (Host Side)

(Module Side)

Top PCB viewed from top

19 GND

18 RX1n

17 RX1p

16 GND

15 RX3n

14 RX3p

13 GND

12 SDA

11 SCL

10 VccRx

9 ResetL

8 ModSelL

7 GND

6 TX4p

5 TX4n

4 GND

3 TX2p

2 TX2n

1 GND

57 GND

56 RX5n

55 RX5p

54 GND

53 RX7n

52 RX7p

51 GND

50 P/VS3

49 P/VS2

48 VccRx1

47 P/VS1

46 P/VS4

45 GND

44 TX8p

43 TX8n

42 GND

41 TX6p

40 TX6n

39 GND

Plug Sequence 1A

Plug Sequence 1B

(Module Side)

Bottom PCB viewed from bottom

Module Card Edge (Host Side)

Plug Sequence 1A

Plug Sequence 1B

Classic QSFP+/QSFP28/QSFP112 Pads

Additional

QSFP-DD/QSFP-DD800 Pads

2 Figure 2: Module pad assignment and layout

1 Table 1- Pad Function Definition

Pad	Logic	Symbol	Description	Plug Sequence4	Notes
1		GND	Ground	1B	1
2	CML-I	Tx2n	Transmitter Inverted Data Input	3B
3	CML-I	Tx2p	Transmitter Non-Inverted Data Input	3B
4		GND	Ground	1B	1
5	CML-I	Tx4n	Transmitter Inverted Data Input	3B
6	CML-I	Tx4p	Transmitter Non-Inverted Data Input	3B
7		GND	Ground	1B	1
8	LVTTL-I	ModSelL	Module Select	3B
9	LVTTL-I	ResetL	Module Reset	3B
10		VccRx	+3.3V Power Supply Receiver	2B	2
11	LVCMOS-I/O	SCL	TWI serial interface clock	3B
12	LVCMOS-I/O	SDA	TWI serial interface data	3B
13		GND	Ground	1B	1
14	CML-O	Rx3p	Receiver Non-Inverted Data Output	3B
15	CML-O	Rx3n	Receiver Inverted Data Output	3B
16		GND	Ground	1B	1
17	CML-O	Rx1p	Receiver Non-Inverted Data Output	3B
18	CML-O	Rx1n	Receiver Inverted Data Output	3B
19		GND	Ground	1B	1
20		GND	Ground	1B	1
21	CML-O	Rx2n	Receiver Inverted Data Output	3B
22	CML-O	Rx2p	Receiver Non-Inverted Data Output	3B
23		GND	Ground	1B	1
24	CML-O	Rx4n	Receiver Inverted Data Output	3B
25	CML-O	Rx4p	Receiver Non-Inverted Data Output	3B
26		GND	Ground	1B	1
27	LVTTL-O	ModPrsL	Module Present	3B
28	LVTTL-O	IntL/RxLOS	Interrupt/optional RxLOS	3B
29		VccTx	+3.3V Power supply transmitter	2B	2
30		Vcc1	+3.3V Power supply	2B	2
31	LVTTL-I	LPMode/TxDis	Low Power mode/optional TX Disable	3B
32		GND	Ground	1B	1
33	CML-I	Tx3p	Transmitter Non-Inverted Data Input	3B
34	CML-I	Tx3n	Transmitter Inverted Data Input	3B
35		GND	Ground	1B	1
36	CML-I	Tx1p	Transmitter Non-Inverted Data Input	3B
37	CML-I	Tx1n	Transmitter Inverted Data Input	3B
38		GND	Ground	1B	1
39		GND	Ground	1A	1
40	CML-I	Tx6n	Transmitter Inverted Data Input	3A
41	CML-I	Tx6p	Transmitter Non-Inverted Data Input	3A
42		GND	Ground	1A	1
43	CML-I	Tx8n	Transmitter Inverted Data Input	3A
44	CML-I	Tx8p	Transmitter Non-Inverted Data Input	3A
45		GND	Ground	1A	1

Pad	Logic	Symbol	Description	Plug Sequence4	Notes
46	LVCMOS/CML-I	P/VS4	Programmable/Module Vendor Specific 4	3A	5
47	LVCMOS/CML-I	P/VS1	Programmable/Module Vendor Specific 1	3A	5
48		VccRx1	3.3V Power Supply	2A	2
49	LVCMOS/CML-O	P/VS2	Programmable/Module Vendor Specific 2	3A	5
50	LVCMOS/CML-O	P/VS3	Programmable/Module Vendor Specific 3	3A	5
51		GND	Ground	1A	1
52	CML-O	Rx7p	Receiver Non-Inverted Data Output	3A
53	CML-O	Rx7n	Receiver Inverted Data Output	3A
54		GND	Ground	1A	1
55	CML-O	Rx5p	Receiver Non-Inverted Data Output	3A
56	CML-O	Rx5n	Receiver Inverted Data Output	3A
57		GND	Ground	1A	1
58		GND	Ground	1A	1
59	CML-O	Rx6n	Receiver Inverted Data Output	3A
60	CML-O	Rx6p	Receiver Non-Inverted Data Output	3A
61		GND	Ground	1A	1
62	CML-O	Rx8n	Receiver Inverted Data Output	3A
63	CML-O	Rx8p	Receiver Non-Inverted Data Output	3A
64		GND	Ground	1A	1
65		NC	No Connect	3A	3
66		Reserved	For future use	3A	3
67		VccTx1	3.3V Power Supply	2A	2
68		Vcc2	3.3V Power Supply	2A	2
69	LVCMOS-I	ePPS/Clock	1PPS PTP clock or reference clock input	3A	6
70		GND	Ground	1A	1
71	CML-I	Tx7p	Transmitter Non-Inverted Data Input	3A
72	CML-I	Tx7n	Transmitter Inverted Data Input	3A
73		GND	Ground	1A	1
74	CML-I	Tx5p	Transmitter Non-Inverted Data Input	3A
75	CML-I	Tx5n	Transmitter Inverted Data Input	3A
76		GND	Ground	1A	1
Note 1: QSFP-DD uses common ground (GND) for all signals and supply (power). All are common within the QSFP- DD module and all module voltages are referenced to this potential unless otherwise noted. Connect these directly to the host board signal-common ground plane. Each connector Gnd contact is rated for a steady state current of 500 mA.
Note 2: VccRx, VccRx1, Vcc1, Vcc2, VccTx and VccTx1 shall be applied concurrently. Supply requirements defined for the host side of the Host Card Edge Connector are listed in Table 13. For power classes 4 and above the module differential loading of input voltage pads must not result in exceeding contact current limits. Each connector Vcc contact is rated for a steady state current of 1500 mA.
Note 3: Reserved pad recommended to be terminated with 10 k to ground on the host. Pad 65 (No Connect) Shall be left unconnected within the module, optionally pad 65 may get terminated with 10 k to ground on the host.
Note 4: Plug Sequence specifies the mating sequence of the host connector and module. The sequence is 1A, 2A, 3A, 1B, 2B, 3B. (See Figure 2 for pad locations) Contact sequence A will make, then break contact with additional QSFP- DD pads. Sequence 1A and 1B will then occur simultaneously, followed by 2A and 2B, followed by 3A and 3B.
Note 5: Full definitions of the P/VSx signals currently under development. For module designs using programmable/vendor specific inputs P/VS1 and P/VS4 signals it is recommended each to be terminated in the module with 10 k For host designs using programmable/vendor specific outputs P/VS2 and P/VS3 signals it is recommended each to be terminated on the host with 10 k
Note 6: for host not implementing ePPS/Clock, it is not necessary to parallel terminate the ePPS/Clock signal to ground on the host. ePPS/Clock already has parallel termination in the module see 4.2.6.

4.2 Low Speed Electrical Hardware Signals ‌
In addition to the TWI serial interface the module has the following low speed signals for control and status:
 ModSelL
 ResetL
 LPMode/TxDis
 ModPrsL
 IntL/RxLOSL
 P/VS1, P/VS2, P/VS3, and P/VS4.
 ePPS/Clock
10

4.2.1 ModSelL ‌
The ModSelL is an input signal that shall be pulled to Vcc in the QSFP-DD/QSFP-DD800 modules (see Table
7). When held low by the host, the module responds to TWI serial communication commands. The ModSelL
allows the use of multiple QSFP-DD/QSFP-DD800 modules on a single TWI interface bus. When ModSelL is
“High”, the module shall not respond to or acknowledge any TWI interface communication from the host. 16

In order to avoid conflicts, the host system shall not attempt TWI interface communications within the ModSelL
de-assert time after any QSFP-DD/QSFP-DD800 modules are deselected. Similarly, the host must wait at least
for the period of the ModSelL assert time before communicating with the newly selected module. The assertion
and de-asserting periods of different modules may overlap as long as the above timing requirements are met. 21

4.2.2 ResetL ‌
The ResetL signal shall be pulled to Vcc in the module (see Table 7). A low level on the ResetL signal for
longer than the minimum pulse length (t_Reset_init) (See Table 9) initiates a complete module reset, returning
all user module settings to their default state. 26

4.2.3 LPMode/TxDis ‌
LPMode/TxDis is a dual-mode input signal from the host operating with active high logic. It shall be pulled
towards Vcc in the module. At power-up or after ResetL is deasserted LPMode/TxDis behaves as LPMode. If
supported, LPMode/TxDis can be configured as TxDis using the TWI interface except during the execution of a
reset. Timing requirements for LPMode/TxDis mode changes are found in, see Table 9. LPMode is used in
the control of the module power mode, see CMIS [5] Chapter 6.3.1.3. 33

When LPMode/TxDis is configured as LPMode, the module behaves as though TxDis=0. By using the
LPMode signal and a combination of the Power_override, Power_set and High_Power_Class_Enable software
control bits the host controls how much power a module can consume. When LPMode/TxDis is configured as
TxDis, the module behaves as though LPMode=0. In this mode LPMode/TxDis when set to 1 or 0 disables or
enables all optical transmitters within the times specified in Table 9. 39

Changing LPMode/TxDis mode from LPMode to TxDis when the LPMode/TxDis state is high disables all
optical transmitters. If the module was in low power mode, then the module transitions out of low power mode
at the same time. If the module is already in high power state (Power Override control bits) with transmitters
already enabled, the module shall disable all optical transmitters. Changing the LPMode/TxDis mode from
LPMode to TxDis when the LPMode/TxDis state is low, simply changes the behavior of the mode of
LPMode/TxDis. The behavior of the module depends on the Power Override control bits. 46

Note that the “soft” functions of TxDis, LPMode, IntL and RxLOSL allow the host to poll or set these values
over the TWI interface as an alternative to monitoring/setting signal values. Asserting either the “hardware” or
“soft bit” (or both) for TxDis or LPMode results in that function being asserted. 50

Editor’s Note: registers to support optional TxDis will be added in future revisions of CMIS.

4.2.4 ModPrsL ‌
ModPrsL shall be pulled up to Vcc Host on the host board and pulled low in the module (see Table 7). The
ModPrsL is asserted “Low” when the module is inserted. The ModPrsL is deasserted “High” when the module
is physically absent from the host connector due to the pull-up resistor on the host board. 7

4.2.5 IntL/RxLOSL ‌
IntL/RxLOSL is a dual-mode active-low, open-collector output signal from the module. It shall be pulled up
towards Vcc on the host board (see Table 7). At power-up or after ResetL is released to high, IntL/RxLOSL is
configured as IntL. When the IntL signal is asserted Low it indicates a change in module state, a possible
module operational fault or a status critical to the host system. The host identifies the source of the interrupt
using the TWI serial interface. The IntL signal is deasserted “High” after all set interrupt flags are read. If dual
mode operation supported, IntL/RxLOSL can be optionally programmed as RxLOSL using the TWI interface
except during the execution of a reset. If the module has no interrupt flags asserted (IntL/RxLOSL is high),
there should be no change in IntL/RxLOSL states after the mode change. 17

If IntL/RxLOSL is configured as RxLOSL, a low indicates that there is a loss of received optical power on at
least one lane. “high” indicates that there is no loss of received optical power. Timing requirements for
IntL/RxLOSL including fast RxLOS mode are found in Table 9. The actual condition of loss of optical receive
power is specified by other governing documents, as the alarm threshold level is application specific. The
module shall pull RxLOSL to low if any lane in a multiple lane module or cable has a LOS condition and shall
release RxLOSL to high only if no lane has a LOS condition. 24

25 Editor’s note: registers to support optional RxLOSL will be added in future revisions of CMIS.

4.2.6 Programmable/Vendor Specific (Optional)‌
QSFP-DD MSA provides 2 input programmable/vendor specific pads (P/VS1, P/VS4) and 2 output
programable/vendor specific pads (P/VS2, P/VS3). Programmable use case also includes vendor proprietary
applications. P/VSx I/O are disabled by default. 31

Editor’s Note - Logic definitions and programmable use cases for P/VSx input/output pads expect to be defined
by QSFP-DD HW MSA and CMIS.

4.2.7 ePPS/Clock PTP Reference Clock (Optional)‌
Host ePPS/Clock The ePPS/Clock input is a programable timing and clock input, that can support
unmodulated 1PPS (1 pulse per second), modulated (1PPS), and reference clock. The ePPS/clock is a
LVCMOS compatible signal with series termination (TBD) on the host board and a parallel termination of at
least 4.7 k in the module. To improve signal integrity for faster clocks (i.e., 156.25 MHz) the parallel
termination can be reduced to as low as 470  and optionally AC coupled. 42

For high-performance Precision Time Protocol (PTP) applications, the ePPS (Enhanced Pulse Per Second)
reference either with 1PPS modulated or unmodulated may be provided from the host to the module for time
synchronization, see Table 2 for advertise capability. This can be used for either offline delay characterization
or real-time delay compensation within the module. The ePPS is used to synchronize tightly the Host Time-of-
Day counter to the module internal Time-of-Day Counter. 48

The ePPS/Clock module input optionally can be configured to provide reference clock to the CDR/DSP, see
Table 2 for advertise capability.

4 Table 2- ePPS/Clock Advertising Capabilities

CMIS Byte Location (TBD)	Bit	Mode Supported
xxxxxx--	00	ePPS/Clock not supported
xxxxxx--	01	ePPS/Clock module supports either 1PPS mode, modulated 1PPS, or clock input for encoding see Table 3
xxxxxx--	10	ePPS/Clock supported TOD (Time of Day)
xxxxxx--	11	ePPS/Clock - Reserved

6 Table 3- ePPS or Clock Modes

CMIS Byte Location (TBD)	Bit	Mode Supported
xxxx--xx	00	RF clock for frequency see table y
xxxx--xx	01	1PPS send as unmodulated pulse duration TBD
xxxx--xx	10	1PPS send as 75%/25% duty cycle on RF modulated clock, for clock frequency see Table 4
xxxx--xx	11	ePPS/Clock - Reserved

8 Table 4- ePPS or Clock Frequency

CMIS Byte Location (TBD)	Bit	Mode Supported
----xxxx	0000	10 MHz
----xxxx	0001	12.5 MHz
----xxxx	0010	20 MHz
----xxxx	0011	24.576 MHz
----xxxx	0100	25 MHz
----xxxx	0101	156.25 MHz
----xxxx	0110-1101	Reserved
----xxxx	1110-1111	Custom

Editor’s Note: registers to support optional ePPS/Clock will be added in future revisions of CMIS.

2 Table 5- Module ePPS/Clock Status Reporting (Required if module supports ePPS/Clock)

CMIS Byte Location (TBD)	Bit	Mode Supported
xxxx--xx	00	ePPS/Clock signals not detected
xxxx--xx	01	1PPS unmodulated signal detected
xxxx--xx	10	1PPS modulated signal detected
xxxx--xx	11	Clock signal detected

CMIS Byte Location (TBD)

Table 6- ePPS RF or Clock Frequency Reporting (Optional)

Bit Mode Supported

----xxxx

0000

0001

0010

0011

0100

0101

0110-1101

1110-1111

10 MHz (ePPS RF)

12.5 MHz (ePPS RF)

20 MHz (ePPS RF)

24.576 MHz (ePPS RF)

25 MHz (ePPS RF)

156.25 MHz (Clock) Reserved

Custom

5
6
7
8
9	4.3 ‌	Examples of QSFP-DD/QSFP-DD800 Host Board Schematic

Figure 3, Figure 4 and Figure 5 show examples of QSFP-DD/QSFP-DD800 host PCB schematics with
connections to CDR and control ICs. An 8-wide electrical/optical interface is shown. Note alternate
electrical/optical interfaces are supported using optical multiplexing (WDM) or electrical multiplexing. 13

Note: Filter capacitors values are informative and application dependent, 0.1 F capacitors should be placed in close proximity to power pads and may be duplicated for individual pads to provide additional high frequency filtering.

Note: Vcc1/Vcc2 may be connected to VccTx/VccTx1 or VccRx/VccRx1 within the module provided the applicable derating of the maximum current limit is used.

2 Figure 3: Example QSFP-DD/QSFP-DD800 host board schematic for Optical Modules

Note: Filter capacitors values are informative and application dependent,

0.1 F capacitors should be placed in close proximity to power pads and may be duplicated for individual pads to provide additional high frequency filtering.

Note: Vcc1/Vcc2 may be connected to VccTx/VccTx1 or VccRx/VccRx1 within the module provided the applicable derating of the maximum current limit is used.

2 Figure 4: Example QSFP-DD/QSFP-DD800 host board schematic for Active Copper Cables Module

Note: Recommended filtering is only valid for dedicated passive copper cable ports. For ports supporting both passive and active modules use recommended filtering from Figure 3 or 4.

2 Figure 5: Example QSFP-DD/QSFP-DD800 host board schematic of Passive Copper Cables Module

4.4 Low Speed Electrical Specification ‌
TWI bus composed of the initiator and the target devices, the initiator controls the bus and the target device
respond to the initiator requests. 4

4.4.1 TWI Logic Levels and Bus Loading ‌
Low speed signaling other than the SCL and SDA interface is based on Low Voltage (LVTTL/LVCMOS)
operating at Vcc. This specification is very similar to SFF-8679 [32] for operation up 400 kHz but this
specification also supports 1 MHz operation. Vcc refers to the generic supply voltages of VccTx, VccRx, Vcc
host or Vcc1. Hosts shall use a pull-up resistor connected to Vcc host on each of the TWI interface SCL
(clock), SDA (data), and all low speed status outputs (see Table 7). The SCL and SDA is a hot plug interface
that may support a bus topology. During module insertion or removal, the module may implement a pre-
charge circuit which prevents corrupting data transfers from other modules that are already using the bus. 13

Tradeoffs between pull-up resistor values, total bus capacitance and the estimated bus rise/fall times are
shown Figure 6.

The QSFP-DD/QSFP-DD800/QSFP112 low speed electrical specifications are given in Table 7, where some of
the parameters are more stringent than JEDEC JESD8C [20]. Implementations compliant to this specification
ensures compatibility between TWI host bus initiator and the TWI target device. 20

21 Table 7- Low Speed Control and Sense Signals

Parameter	Symbol	Min	Max	Unit	Condition
SCL and SDA	VOL	0	0.4	V	IOL (max)=3 mA for fast mode, 20 mA for Fast-mode plus
SCL and SDA	VIL	-0.3	Vcc*0.3	V
SCL and SDA	VIH	Vcc*0.7	Vcc+0.5	V
Capacitance for SCL and SDA I/O signal	Ci		14	pF
Total bus capacitive load for SCL and SDA	Cb		100	pF	For 400 kHz clock rate use 3 k pullup resistor, max. For 1000 kHz clock rate refer to Figure 6.
Total bus capacitive load for SCL and SDA	Cb		200	pF	For 400 kHz clock rate use 1.6 k pullup resistor, max. For 1000 kHz clock rate refer to Figure 6.
LPMode/TxDis, ResetL, ModSelL and ePPS/Clock	VIL	-0.3	0.8	V
LPMode/TxDis, ResetL, ModSelL and ePPS/Clock	VIH	2	Vcc+0.3	V
P/VS[1, 2, 3, 4]	VIL		TBD	V
P/VS[1, 2, 3, 4]	VIH		TBD
LPMode, ResetL and ModSelL	\|Iin\|		360	A	0V<Vin<Vcc
ePPS/Clock	\|Iin\|		6.5	mA	0V<Vin<Vcc
P/VS[1, 2, 3, 4]	\|Iin\|		TBD
IntL/RxLOS	VOL	0	0.4	V	IOL=2.0 mA
IntL/RxLOS	VOH	Vcc-0.5	Vcc+0.3	V	10 k pull-up to Host Vcc
ModPrsL	VOL	0	0.4	V	IOL=2.0 mA
ModPrsL	VOH				ModPrsL can be implemented as a short-circuit to GND on the module

3 Figure 6: SDA/SCL options for pull-up resistor, bus capacitance and rise/fall times

4.5 Management Interface ‌
A management interface, as already commonly used in other form factors like QSFP, SFP, and CDFP, is
specified in order to enable flexible use of the module by the user. The QSFP-DD/QSFP-DD800 memory map
are based on “Common Management Interface Specification (CMIS)” [5]. Some timing requirements are
critical, especially for a multi-lanes device, so the interface speed may optionally be increased. Byte 00h on
the Lower Page or Address 128 Page 00h is used to indicate the use of the QSFP-DD/QSFP-DD800 memory
map rather than the QSFP memory map. When a QSFP+ module is inserted into a QSFP-DD/QSFP-DD800
port the host must determine which memory map to use (e.g., SFF-8636 [30] or CMIS [5]) based on the
QSFP+ identifier at Byte 00h on the Lower Page or Address 128 Page 00h. Operation of QSFP+ in QSFP-
DD/QSFP-DD800 host is outside the scope of this document. 16

In some applications, muxing or demuxing may occur in the module. In this specification, all references to lane
numbers are based on the electrical connector interface lanes, unless otherwise indicated. In cases where a
status or control aspect is applicable only to lanes after muxing or demuxing has occurred, the status or control
is intended to apply to all lanes in the mux group, unless otherwise indicated. 21

Low speed signaling is based on Low Voltage CMOS (LVCMOS) operating at Vcc, [20]. Hosts shall use a pull-
up resistor connected to Vcc_host on the TWI interface SCL (clock) and SDA (Data) signals. Detailed electrical
specifications are given in 4.4. Timing specifications for management functionality involving electrical low
speed signals are found are given in Table 9. 26

27 Nomenclature for all registers more than 1 bit long is MSB-LSB. 28

4.5.1 Management Interface Timing Specification ‌
The timing parameters for the TWI interface (TWI) to the QSFP-DD/QSFP-DD800 module memory transaction
timings are shown in Figure 7 and specified in Table 8 and is compatible with I2C [21]. The default clock rate
is a maximum of 400 kHz with an option to support up to a maximum of 1 MHz. This clause closely follows the
QSFP+ SFF-8636 [30] specification with the addition of Fast Mode+. This specification also defines tBUF
timing, tWR timing, tNACK timing, tBPC timing. 7

Figure 7: TWI Timing Diagram

2 Table 8- Management Interface timing parameters

TWI Modes		Fast Mode (400 kHz)		Fast Mode+ (1 MHz)
Parameter	Symbol	Min	Max	Min	Max	Unit	Conditions
Clock Frequency	fSCL	0	400	0	1000	kHz
Clock Pulse Width Low	tLOW	1.3		0.50		µs
Clock Pulse Width High	tHIGH	0.6		0.26		µs
Time bus free before new transmission can start	tBUF	20		20		µs	Between STOP and START and between ACK and ReStart
START Hold Time	tHD.STA	0.6		0.26		µs	The delay required between SDA becoming low and SCL starting to go low in a START
START Setup Time	tSU.STA	0.6		0.26		µs	The delay required between SCL becoming high and SDA starting to go low in a START
Data In Hold Time	tHD.DAT	0		0		µs
Data In Setup Time	tSU.DAT	0.1		0.1		µs
Input Rise Time	tR		300		120	ns	From (VL,MAX=0.3Vcc) to (VIH,MIN=0.7Vcc), see Figure 6
Input Fall Time	tF		300		120	ns	From (VIH,MIN=0.7Vcc) to (VIL,MAX=0.3Vcc), see Figure 6
STOP Setup Time	tSU.STO	0.6		0.26		µs
STOP Hold Time	tHD.STO	0.6		0.26		µs
Aborted sequence – bus release	Deselect _Abort		2		2	ms	Delay from a host de-asserting ModSelL (at any point in a bus sequence) to the QSFP-DD module releasing SCL and SDA
ModSelL Setup Time1	tSU. ModSelL	2		2		ms	ModSelL Setup Time is the setup time on the select line before the start of a host initiated TWI serial bus sequence.
ModSelL Hold Time1	tHD. ModSelL	2		2		ms	ModSelL Hold Time is the delay from completion of a TWI serial bus sequence to changes of module select status.
TWI Serial Interface Clock Holdoff “Clock Stretching”	T_clock_ hold		500		500	µs	Time the QSFP-DD module may hold the SCL line low before continuing with a read or write operation.
Complete Single or Sequential Write to non- volatile registers	tWR		80		80	ms	Time to complete a Single or Sequential Write to non-volatile registers.
Accept a single or sequential write to volatile memory	tNACK		10		10	ms	Time to complete a Single or Sequential Write to volatile registers.
Time to complete a memory bank/page	tBPC		10		10	ms	Time to complete a memory bank and/or page change.
Endurance (Write Cycles)		50k		50k		cycles	Module Case Temperature = 70 ºC
Note 1: CMIS management registers can be read to determine alternate ModSelL set up and hold times. See CMIS 8.4.5, Durations Advertising.

The TWI serial interface address of the QSFP-DD module is 1010000X (A0h). In order to allow access to
multiple QSFP-DD/QSFP-DD800 modules on the same TWI serial bus, the QSFP-DD/QSFP-DD800 includes
a module select pad, ModSelL. This input (which is pulled high, deselected in the module) must be held low by
the host to select the module of interest and allow communication over the TWI serial interface. The module
must not respond to or accept TWI serial bus instructions unless it is selected. 6

Before initiating a TWI serial bus communication, the host shall provide setup time on the ModSelL line of all
modules on the TWI bus. The host shall not change the ModSelL line of any module until the TWI serial bus
communication is complete and the hold time requirement is satisfied. 10

4.5.2 Timing for soft control and status functions ‌
Timing for QSFP-DD/QSFP-DD800 soft control status functions are described in Table 9. Squelch and disable
timings are defined in Table 10. 14

Table 9- Timing for QSFP-DD soft control and status functions

Parameter	Symbol	Min	Max	Unit	Conditions
MgmtInitDuration	Max MgmtInit Duration		2000	ms	Time from power on1, hot plug or rising edge of reset until until the high to low SDA transition of the Start condition for the first acknowledged TWI transaction.
ResetL Assert Time	t_reset_init	10		µs	Minimum pulse time on the ResetL signal to initiate a module reset.
Int/RxLOS Mode Change	t_IntL/RxLOSL		100	ms	Time to change between IntL and RxLOSL modes of the dual- mode signal IntL/RxLOSL.
LPMode/TxDis mode change time	t_LPMode/TxDis		100	ms	Time to change between LPMode and TxDis modes of LPMode/TxDis.
IntL Assert Time	ton_IntL		200	ms	Time from occurrence of condition triggering IntL until Vout:IntL=Vol.
IntL Deassert Time	toff_IntL		500	µs	Time from clear on read2 operation of associated flag until Vout:IntL=Voh. This includes deassert times for Rx LOS, Tx Fault and other flag bits.
RxLOS Assert Time	ton_los		100	ms	Time from Rx LOS condition present to Rx LOS bit set (value = 1b) and IntL asserted 3.
Rx LOS Assert Time (optional fast mode)	ton_losf		1	ms	Time from Rx LOS state to Rx LOS bit set (value = 1b) and IntL asserted 3.
RxLOS Deassert Time (optional fast mode)	toff_f_LOS		3	ms	Optional fast mode is advertised via the CMIS. Time from optical signal above the LOS deassert threshold to when the module releases the RxLOSL signal to high.
TX Disable Assert Time	ton_TxDis		100	ms	Time from Tx Disable bit set to 1 until optical output falls below 10% of nominal.
TX Disable Assert Time (optional fast mode)	ton_f_TxDis		3	ms	Optional fast mode is advertised via CMIS. Time from TxDis signal high to the optical output reaching the disabled level.
TX Disable Deassert Time	toff_TxDis		400	ms	Time from Tx Disable bit cleared to 1 until optical output rises above 90% of nominal 4.
Tx Fault Assert Time	ton_Txfault		200	ms	Time from Tx Fault state to Tx Fault bit set (value=1b) and IntL asserted.

Flag Assert Time	ton_flag	200	ms	Time from occurrence of condition triggering flag to associated flag bit set (value=1b) and IntL asserted.
Mask Assert Time	ton_mask	100	ms	Time from mask bit set (value=1b) 5 until associated IntL assertion is inhibited.
Mask Deassert Time	toff_mask	100	ms	Time from mask bit cleared (value=0b) 5 until associated IntL operation resumes
Data Path Tx Turn On Max Duration6	DataPathTxTurnOn_MaxDuration			see CMIS memory P01h: B168
Data Path Tx Turn Off Max Duration6	DataPathTxTurnOff_MaxDuration			see CMIS memory P01h: B168
Data Path Deinit Max Duration6	DataPathDeinit_MaxDuration			see CMIS memory P01h: B144
Data Path Init Max Duration6	DataPathInit_MaxDuration			see CMIS memory P01h: B144
Module Pwr Up Max Duration7	ModulePwrUp_MaxDuration			see CMIS memory P01h: B167
Module Pwr Dn Max Duration7	ModulePwrDn_MaxDuration			see CMIS memory P01h: B167
Notes: 1. Power on is defined as the instant when supply voltages reach and remain at or above the minimum level specified in Table 13.
Measured from low to high SDA edge of the Stop condition of the read transaction. Rx LOS condition is defined at the optical input by the relevant standard. Tx Squelch Deassert time is longer than SFF-8679 [32].
5. Measured from low to high SDA edge of the Stop condition of the write transaction.
Measured from the low to high SDA edge of the Stop condition of the Write transaction until the IntL for the state change Vout:IntL=Vol, unless the module advertises a less than 1 ms duration in which case there is no defined measurement. Measured from the low to high SDA edge of the Stop condition of the Write transaction until the IntL for the state change Vout:IntL=Vol.

Table 10- I/O Timing for Squelch & Disable

Parameter	Symbol	Max	Unit	Conditions
Rx Squelch Assert Time	ton_Rxsq	15	ms	Time from loss of Rx input signal until the squelched output condition is reached, see 4.6.1.
Tx Squelch Assert Time	ton_Txsq	400	ms	Time from loss of Tx input signal until the squelched output condition is reached, see 4.6.2.
Tx Squelch Deassert Time	toff_Txsq	1.5	s	Tx squelch deassert is system and implementation dependent, see also 4.6.2.
Tx Disable Assert Time	ton_txdis	100	ms	Time from the stop condition of the Tx Disable write sequence1 until optical output falls below 10% of nominal.
Tx Disable Assert Time (optional fast mode)	ton_txdisf	3	ms	Time from Tx Disable bit set (value = 1b)1 until optical output falls below 10% of nominal, see notes 2 and 3.
Tx Disable Deassert Time	toff_txdis	400	ms	Time from Tx Disable bit cleared (value = 0b)1 until optical output rises above 90% of nominal, see notes 2, and 3.
Tx Disable Deassert Time (optional fast mode)	toff_txdisf	10	ms	Time from Tx Disable bit cleared (value = 0b)1 until optical output rises above 90% of nominal, see notes 2 and 3.
Rx Output Disable Assert Time	ton_rxdis	100	ms	Time from Rx Output Disable bit set (value = 1b)1 until Rx output falls below 10% of nominal
Rx Output Disable Deassert Time	toff_rxdis	100	ms	Time from Rx Output Disable bit cleared (value = 0b)1 until Rx output rises above 90% of nominal.
Squelch Disable Assert Time	ton_sqdis	100	ms	This applies to Rx and Tx Squelch and is the time from bit set (value = 0b)1 until squelch functionality is disabled.
Squelch Disable Deassert Time	toff_sqdis	100	ms	This applies to Rx and Tx Squelch and is the time from bit cleared (value = 0b)1 until squelch functionality is enabled.
Notes: Measured from LOW to HIGH SDA signal transition of the STOP condition of the write transaction. CMIS 4.0 and beyond the listed values are superseded by the advertised DataPathTxTurnOff_MaxDuration and DataPathTxTurnOn_MaxDuration times in P01h.168. Listed values place a limit on the DataPathTxTurnOff_MaxDuration and DataPathTxTurnOn_MaxDuration times (P01h.168) that can be advertised by such modules (for CMIS 4.0 and beyond).

4.6 High Speed Electrical Specification ‌
For detailed QSFP-DD electrical specifications for operation up to 29 GBd see e.g., IEEE Std 802.3-2018
Annex 86A, Annex 83E, Annex 120C, or Annex 120E [15]; Fibre Channel FC-PI-6 [1], FC-PI-7 [2]; OIF CEI 4.0
[22]; InfiniBand FDR, EDR, and HDR specifications [19]. For detailed QSFP-DD-800 electrical specifications
for operation up to 58 GBd see e.g., IEEE P802.3ck Annex 120G [17]; Fibre Channel FC-PI-8 [3]; OIF CEI-
112G-VSR [22]; InfiniBand NDR specifications [19].

Partial or complete squelch specifications may be provided in the appropriate specification. Where squelch is
not fully defined by the appropriate specification, the recommendations of the following subsections 4.6.1 and

4.6.2 may be used.

12 4.6.1 Rx(n)(p/n)‌

Rx(n)(p/n) are QSFP-DD/QSFP-DD800 module receiver data outputs. Rx(n)(p/n) are AC-coupled 100 Ohm
differential lines that should be terminated with 100 Ohm differentially at the Host ASIC(SerDes). The AC
coupling is inside the QSFP-DD/QSFP-DD800/QSFP112 modules and not required on the Host board. When
properly terminated, the differential voltage swing shall be less than or equal to 900 mVpp or as defined by the
relevant standard, or whichever is less. 18

Output squelch for loss of optical input signal, hereafter Rx Squelch, is required and shall function as follows.
In the event of the Rx input signal on any optical port becoming equal to or less than the level required to
assert LOS, then the receiver output(s) associated with that Rx port shall be squelched. A single Rx optical
port can be associated with more than one Rx output as shown in Table 24. In the squelched state output
impedance levels are maintained while the differential voltage amplitude shall be less than 50 mVpp. 24

In normal operation the default case has Rx Squelch active. Rx Squelch can be deactivated using Rx Squelch
Disable through the TWI serial interface. Rx Squelch Disable is an optional function.
4.6.2 Tx(n)(p/n)‌
Tx(n)(p/n) are QSFP-DD module transmitter data inputs. They are AC-coupled 100  differential lines with
100 Ohm differential terminations inside the QSFP-DD/QSFP-DD800/QSFP112 optical module. The AC
coupling is implemented inside the QSFP-DD optical module and not required on the Host board. 31

Output squelch for loss of electrical signal, hereafter Tx Squelch, is an optional function. Where implemented it
shall function as follows. In the event of the differential, peak-to-peak electrical signal amplitude on any
electrical input lane becoming less than the TX Squelch Levels specified in Table 11 when terminated in to 100
 differential, then the transmitter optical output associated with that electrical input lane shall be squelched
and the associated TxLOS flag set. If multiple electrical input lanes are associated with the same optical output
lane, the loss of any of the incoming electrical input lanes causes the optical output lane to be squelched. 38

39 Table 11- TX Squelch Levels

Data Rate	Levels	Unit
OIF 28G-VSR/IEEE CL83E	70	mV 1
OIF 56G-VSR/IEEE CL120E	70	mV 1
OIF 112G-VSR/IEEE CL120G	50	mV 1
1. Differential peak-peak.

For applications, e.g., Ethernet, where the transmitter off condition is defined in terms of average power,
squelching by disabling the transmitter is recommended and for applications, e.g., InfiniBand, where the
transmitter off condition is defined in terms of OMA, squelching the transmitter by setting the OMA to a low
level is recommended.

In module operation, where Tx Squelch is implemented, the default case has Tx Squelch active. Tx Squelch
can be deactivated using Tx Squelch Disable through the TWI serial interface. Tx Squelch and Tx Squelch
Disable are optional functions. 4

4.7 Power Requirements‌
The power supply has six designated pads, VccTx, VccTx1, Vcc1, Vcc2, VccRx, VccRx1 in the connector.
VccRx, VccRx1, Vcc1, Vcc2, VccTx and VccTx1 may be internally connected within the module in any
combination at the discretion of the module vendor. Power is applied concurrently to these pads. 9

A host board together with the QSFP-DD/QSFP-DD800 module(s) forms an integrated power system. The host
supplies stable power to the module. The module limits electrical noise coupled back into the host system and
limits inrush charge/current during hot plug insertion or module state transitions. 13

All power supply requirements in Table 13 shall be met at the maximum power supply current. No power
sequencing of the power supply is required of the host system since the module sequences the contacts in the
order of ground, supply and signals during insertion. 17

4.7.1 Power Classes and Maximum Power Consumption ‌
There are two power modes: Low Power Mode and High Power Mode, and eight power classes, Class 1 -
Class 8. Module power classes are defined in Table 12 and module power specifications are provided in Table
13.

Since a wide range of module power classes exist, to avoid exceeding the system power supply limits and
cooling capacity when a module is inserted into a system designed to accommodate only low power
consumption modules, it is recommended that host systems designed to accommodate only low power
consumption modules also implement the state machine defined in the CMIS [5] and identify the power class of
the module before allowing the module to go into High Power Mode, where power class 8 requires reading
CMIS (Page00, Byte 201) to determine actual power consumption. This is to avoid exceeding the host system
power supply limits and cooling capacity when a module exceeding the power class supported by the system is
inserted.

32 Table 12- Power Classes

Power Class	Max Power (W)	CMIS Register
1	1.5	Direct readout of Page 00h Byte 200[000xxxxx]
2	3.5	Direct readout of Page 00h Byte 200[001xxxxx]
3	7.0	Direct readout of Page 00h Byte 200[010xxxxx]
4	8.0	Direct readout of Page 00h Byte 200[011xxxxx]
5	10	Direct readout of Page 00h Byte 200[100xxxxx]
6	12	Direct readout of Page 00h Byte 200[101xxxxx]
7	14	Direct readout of Page 00h Byte 200[110xxxxx]
8 1	>14	Direct readout of Page 00h Byte 200[111xxxxx]
Note: 1. When a module reports power class 8 the host must read CMIS Page 00h Byte 201 to determine module power dissipation. Please see CMIS Byte 201 register definition for more information.

In general, the higher power classification levels are associated with higher data rates and longer reaches. The
system designer is responsible for ensuring that the maximum case temperature does not exceed the case
temperature requirements.

4.7.2 Host Board Power Supply Filtering ‌
The specification of the host power supply filtering network is beyond the scope of this specification,
particularly because of the wide range of module Power Classes. During power transient events, the host
should ensure that any neighboring modules sharing the same supply stay within their specified supply voltage
limits. The host should also ensure that the intrinsic noise of the power rail is filtered in order to guarantee the
correct operation of the optical modules. An example reference power supply filter is shown in Figure 8.

8 Figure 8: Reference Power Supply Filter for Module Testing

Any voltage drop across a filter network on the host is counted against the host DC set point accuracy
specification. System designers should choose components with appropriate DCR and ESR, to minimize the
voltage drop and the amount of noise coupled to the module. Hosts supporting higher power classes modules

13 may require additional design considerations, in order to minimize the voltage drop and the amount of noise

14 coupled to the module. 15

The specifications for the power supply are shown in Table 13. The limits in Table 13 apply to the combined
current that flows through all inductors in the power supply filter (represents host Icc current in Figure 8).
Inrush current shall be measured with the appropriate equipment, such as current probes or shunt resistors.
The test equipment shall provide enough bandwidth, vertical resolution, SNR and memory depth, in order to
capture properly all the power events. 21

4.7.3 Module Power Supply Specification ‌
In order to avoid exceeding the host system power capacity, if the host pulls LPMode high, upon hot-plug,
power cycle or reset, QSFP-DD/QSFP-DD800 modules shall power up in Low Power Mode. If the host pulls
LPMode low, the module will proceed to High Power Mode without host management intervention. Figure 9
shows waveforms for maximum instantaneous, sustained and steady state currents for Low Power and High
Power modes. Specification values for maximum instantaneous, sustained and steady state currents at each
power classes are given in Table 13. 29

The module shall not be affected by the instantaneous variations of the power supply caused by its own
current drawing profile during all power transient events. The module shall support instantaneous power
supply Vcc variations with a slew rate up to 175 mV/ms. No traffic hits or TWI errors shall be observed during

Vcc variations.

Table 13- Power supply specifications, instantaneous, sustained, and steady state current limits

Parameter	Symbol	Min	Nom	Max	Unit
Power supply voltages VccTx, VccTx1, VccRx, VccRx1, Vcc1 & Vcc2 including ripple, droop and noise below 100 kHz1		3.135	3.3	3.465	V
Module inrush - instantaneous peak duration2	T_ip			50	µs
Module inrush - initialization time2	T_init			500	ms
Low Power Mode for all modules and Power Class 1 module
Power Consumption Class	P_0			1.5	W
Instantaneous peak current at hot plug	Icc_ip_lp	-	-	600	mA
Sustained peak current at hot plug	Icc_sp_lp	-	-	495	mA
Steady state current	Icc_lp	See Note 3			mA
High Power Mode Power Class 2 module
Power Consumption Class	P_2			3.5	W
Instantaneous peak current	Icc_ip_2	-	-	1400	mA
Sustained peak current	Icc_sp_2	-	-	1155	mA
Steady state current	Icc_2	See Note 3			mA
High Power Mode Power Class 3 module
Power Consumption Class	P_3			7	W
Instantaneous peak current	Icc_ip_3	-	-	2800	mA
Sustained peak current	Icc_sp_3	-	-	2310	mA
Steady state current	Icc_3	See Note 3			mA
High Power Mode Power Class 4 module
Power Consumption Class	P_4			8	W
Instantaneous peak current	Icc_ip_4	-	-	3200	mA
Sustained peak current	Icc_sp_4	-	-	2640	mA
Steady state current	Icc_4	See Note 3			mA
High Power Mode Power Class 5 module
Power Consumption Class	P_5			10	W
Instantaneous peak current	Icc_ip_5	-	-	4000	mA
Sustained peak current	Icc_sp_5	-	-	3300	mA
Steady state current	Icc_5	See Note 3			mA
High Power Mode Power Class 6 module
Power Consumption Class	P_6			12	W
Instantaneous peak current	Icc_ip_6	-	-	4800	mA
Sustained peak current	Icc_sp_6	-	-	3960	mA
Steady state current	Icc_6	See Note 3			mA
High Power Mode Power Class 7 module
Power Consumption Class	P_7			14	W
Instantaneous peak current	Icc_ip_7	-	-	5600	mA
Sustained peak current	Icc_sp_7	-	-	4620	mA
Steady state current	Icc_7	See Note 3			mA
High Power Mode Power Class 8 module
Power Consumption Class	P_84			>14	W
Instantaneous peak current	Icc_ip_8	-	-	P_8/2.5	A
Sustained peak current	Icc_sp_8	-	-	P_8/3.03	A
Steady state current	Icc_8	-	-	9	A
Notes: 1. Measured at VccTx, VccTx1, VccRx, VccRx1, Vcc1 and Vcc2. 2: T_ip and T_init are test conditions for measuring inrush current and not characteristics of the module 3: The module must stay within its declared power class. 4: P_8 is the module power dissipation reported by CMIS Byte 201.

Figure 9: Instantaneous and sustained peak currents for Icc Host (see Table 13)

4.7.4 Host Board Power Supply Noise Output ‌
The host noise output on Vcc1/Vcc2, VccTx/VccTx1, and VccRx/VccRx1 supplies are defined with resistive
loads that draws the maximum rated power supported by the host power class, see Figure 10. The resistive
loads are connected in place of the module between Vcc1/Vcc2, VccTx/VccTx1, and VccRx/VccRx1 and the
Vee. When the noise is measured on the three voltage rails Vcc1/Vcc2, VccTx/VccTx1, and VccRx/VccRx1,
the noise is measured independently on each rail, and the two voltage rails not being tested are left open
circuit. Host power supply limits are given in Table 12. The noise power spectrum is measured for each of the
3 rails then integrated from 40 Hz to 10 MHz and converted to a voltage, eN_Host, with limit specified in Table
14.

2 Figure 10: Host Noise Output Measuremnt

4.7.5 Module Power Supply Noise Output ‌
The QSFP-DD/QSFP-DD800 modules, when plugged into a reference module compliance board shall
generate noise less than the value in Table 14. The module must pass module power supply noise output test
in all operating modes. This test ensures the module will not couple excessive noise from in- side the module
back onto the host board. A power meter technique, or a spectrum analyzer technique with integration of the
spectrum, may be used. 10

The RMS module noise voltage output is defined in the frequency band from 40 Hz to 10 MHz. Module noise
output shall be measured with an appropriate probing technique at point X, see Figure 11 and must meet limits
given in Table 14. The module must pass module power supply noise output test in all operating modes. This
test ensures the module will not couple excessive noise from inside the module back onto the host board.

16 Figure 11: Module Noise Output Measuremnt

4.7.6 Module Power Supply Noise Tolerance ‌
The QSFP-DD/QSFP-DD800 modules shall meet all requirements and operate within the design specifications
in the presence of a reference noise waveform described in Table 14 superimposed on the DC voltage. The
reference noise waveform consists of a sinusoidal 40 Hz to 10 MHz noise generated by Osc1 and added to
Vcc PSU, see Figure 12. This emulates the worst-case noise that the module must tolerate and operate within
the design specifications. The reference noise is generated by Osc1 and amplified by the Power OpAmp then
added to Vcc PSU through a Bias-T, see Figure 12. Example of suitable Power OpAmp are Analog Devices
ADA4870 (EOL and may not be available) and LT1210, and TI THS3491. With power supply filter components
removed, point X measures the noise voltage applied to the module. To facilitate power supply tolerance
testing at frequencies < ~100 kHz due to Power OpAmp interaction with PSU and low frequency response of
the Bias-T, it is recommended to use noise source Osc2 modulating PSU sense line to generate sinusoidal
noise directly on the PSU output, see Figure 13. Osc2 amplitude level is adjusted while observing point X
amplitude level as defined in Table 14 for module in low power and high-power modes. To modulate the PSU
sense lines, the PSU must have high speed sense tracking. An example of PSU with high-speed sense
tracking are TI TPSM5D1806 and Keysight N6700 with N6781/N6782 plugins. 16

For modules without or with limited input stage power filtering one may measure the applied noise to the
module by measuring point X directly while the module is active and either in low or high-power modes. To
compensate for input stage power filtering in the module, the DUT module is replaced with a resistive load
drawing equivalent current of a module configured in low power mode, the DUT module is then replaced with a
resistive load drawing equivalent current of a module configured in high power mode. Osc1 and Osc2 are
adjusted to produce maximum PSNR level as defined in Table 14 at point X with resistive loads drawing the
same power as the module in low and high-power modes. The resistive loads are then replaced with the DUT
module with the same Osc1/Osc2 amplitude settings that produced the max PSNR with the resistive loads. 25

Notes: An appropriate probing technique is required for noise measurement at point X. For modules with
limited or no decoupling directly connected to host PSU, the PSNR can be directly measured at point X with
module plugged into the host for module operating in low power and high power modes. Osc1 or Osc2 are
adjusted to provide maximum PSNR at point X for a given module in low power and full power modes. 30

32 Table 14- Power Supply Output Noise and Tolerance Specifications

Parameter	Symbol	Min	Nom	Max	Unit
Host RMS noise output 40 Hz-10 MHz (eN_Host)1				25	mV
Module RMS noise output 40 Hz - 10 MHz 2				30	mV
Module sinusoidal power supply noise tolerance 40 Hz - 10 MHz (p-p) 2, 3	PSNRmod			66	mV
Host must be tested for all supported power classes Module must be test at low and high power modes Recommended test frequencies: 40, 50, 60, 70, 80, 90 Hz 100, 200, 300, 400, 500, 600, 700, 800, 900 Hz 1, 2, 3, 4, 5, 6, 7, 8, 9 kHz 10, 20, 30, 40, 50, 60, 70, 80, 90 kHz 100, 200, 300, 400, 500, 600, 700, 800, 900 kHz 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 MHz.

2 Figure 12: Module High Frequency Noise Tolerance

5 Figure 13: Module Low Frequency Noise Tolerance

4.8 ESD ‌
Where ESD performance is not otherwise specified, e.g., in the Ethernet specification, the QSFP-DD/QSFP-
DD800 modules shall meet ESD requirements given in EN61000-4-2, criterion B test specification when
installed in a properly grounded cage and chassis. The units are subjected to 15 kV air discharges during
operation and 8 kV direct contact discharges to the case. All the QSFP-DD/QSFP-DD800 modules and host
pads including high speed signal pads shall withstand 1000 V electrostatic discharge based on Human Body
Model per JEDEC JS-001 [9 ][20] and IEC EN61000-4-2 [8].
4.9 Clocking Considerations ‌
4.9.1 Data Path Description ‌
Within a module, host electrical and module media lanes are grouped together into a logical concept called a
data path. A data path is intended to represent a group of lanes over which a block of data is distributed that
will be powered up or down and initialized together. Some examples include a 100GAUI-4 to 100GBASE-SR4
module implementation, where the data path would include four host electrical lanes and four module media
lanes, or a 400GAUI-8 to 400GBASE-DR4 module implementation, where the data path would include eight
host electrical lanes and four module media lanes. 16

4.9.2 TX Clocking Considerations ‌
Within a given Tx data path the host is responsible for ensuring that all electrical lanes delivered to the module
are frequency synchronous (sourced from the same clock domain). If a module supports multiple Tx data paths
running concurrently, the different Tx data paths can either all be in a single clock domain or separate clock
domains. The module advertises which of these two modes it supports via the management registers. 22

If the module supports multiple Tx data paths running concurrently in a single clock domain, the module shall
ensure that active Tx data paths continue to operate undisturbed even as other Tx data paths (and their
associated Tx input lanes) are enabled/disabled by the host. 26

4.9.3 Rx Clocking Considerations ‌
Within a given Rx data path all lanes received on the module media interface are required to be frequency
synchronous (sourced from the same clock domain). If a module supports multiple Rx data paths running
concurrently, the module shall allow the different Rx data paths to be asynchronous from each other (sourced
from separate clock domains). 32

5 QSFP112 Electrical Specification and Management Interface Timing ‌
This Chapter contains signal definitions and requirements that are specific to the for QSFP112 hosts and
modules. Hosts designed to the requirements of this chapter accept modules in the QSFP family as well as
QSFP112 modules. Compliance points for electrical measurements are defined in the applicable industry
standards.

5.1 QSFP112 Electrical Connector ‌
The QSFP112 module edge connector consists of a single paddle card with 19 pads on the top and 19 pads
on the bottom of the paddle card for a total of 38 pads. The QSFP112 pads are for 100 Gb/s operation but are
compatible with the classic QSFP+/QSFP28 [32] modules with exception that the current rating for Vcc, VccRx,
and VccTx contacts are increased to 1.5 A. 12

13 The pads are designed for a sequenced mating:

First mate “1”– ground pads
Second mate “2”– power pads
Third mate “3”– signal pads

Where color green identifies ground pads, color red identifies power pads, color orange identifies low speed
signal/control pads, and color blue identifies high speed I/O pads. 21

The QSFP+/QSFP28/QSFP112 pads mates in following sequential order ground, power, and signals, see
Table 15.

Figure 14 shows the signal symbols and pad numbering for the QSFP112 module edge connectors. The
diagram shows the module PCB edge as a top and bottom view. There are 38 pads intended for high speed
signals, low speed signals, power and ground connections. 28

Top PCB viewed from top

GND TX1n TX1p GND TX3n TX3p GND

LPMode/TxDis Vcc1

VccTx IntL/RxLOS ModPrsL GND

RX4p RX4n GND RX2p RX2n GND

Plug Sequence 1

Module Card Edge (Host Side)

(Module Side)

Bottom PCB viewed from bottom

GND RX1n RX1p GND RX3n RX3p GND SDA SCL

VccRx ResetL ModSelL GND TX4p TX4n GND TX2p TX2n GND

Module Card Edge (Host Side)

(Module Side)

Plug Sequence 1

Classic QSFP+/QSFP28/QSFP112 Pads

2 Figure 14: QSFP112 module pad assignment and layout

1 Table 15- QSFP112 Pad Function Definition

Pad	Logic	Symbol	Description	Plug Sequence4	Notes
1		GND	Ground	1	1
2	CML-I	Tx2n	Transmitter Inverted Data Input	3
3	CML-I	Tx2p	Transmitter Non-Inverted Data Input	3
4		GND	Ground	1	1
5	CML-I	Tx4n	Transmitter Inverted Data Input	3
6	CML-I	Tx4p	Transmitter Non-Inverted Data Input	3
7		GND	Ground	1	1
8	LVTTL-I	ModSelL	Module Select	3
9	LVTTL-I	ResetL	Module Reset	3
10		VccRx	+3.3V Power Supply Receiver	2	2
11	LVCMOS-I/O	SCL	TWI serial interface clock	3
12	LVCMOS-I/O	SDA	TWI serial interface data	3
13		GND	Ground	1	1
14	CML-O	Rx3p	Receiver Non-Inverted Data Output	3
15	CML-O	Rx3n	Receiver Inverted Data Output	3
16		GND	Ground	1	1
17	CML-O	Rx1p	Receiver Non-Inverted Data Output	3
18	CML-O	Rx1n	Receiver Inverted Data Output	3
19		GND	Ground	1	1
20		GND	Ground	1	1
21	CML-O	Rx2n	Receiver Inverted Data Output	3
22	CML-O	Rx2p	Receiver Non-Inverted Data Output	3
23		GND	Ground	1	1
24	CML-O	Rx4n	Receiver Inverted Data Output	3
25	CML-O	Rx4p	Receiver Non-Inverted Data Output	3
26		GND	Ground	1	1
27	LVTTL-O	ModPrsL	Module Present	3
28	LVTTL-O	IntL/ RxLOS	Interrupt/optional RxLOS	3
29		VccTx	+3.3V Power supply transmitter	2	2
30		Vcc1	+3.3V Power supply	2	2
31	LVTTL-I	LPMode/ TxDis	Low Power mode/optional TX Disable	3
32		GND	Ground	1	1
33	CML-I	Tx3p	Transmitter Non-Inverted Data Input	3
34	CML-I	Tx3n	Transmitter Inverted Data Input	3
35		GND	Ground	1	1
36	CML-I	Tx1p	Transmitter Non-Inverted Data Input	3
37	CML-I	Tx1n	Transmitter Inverted Data Input	3
38		GND	Ground	1	1
Note 1: QSFP112 uses common ground (GND) for all signals and supply (power). All are common within the QSFP- DD module and all module voltages are referenced to this potential unless otherwise noted. Connect these directly to the host board signal-common ground plane. Each connector Gnd contact is rated for a maximum current of 500 mA. Note 2: VccRx, Vcc1, and VccTx shall be applied concurrently. Supply requirements defined for the host side of the Host Card Edge Connector are listed in Table 13. For power classes 4 and above the module differential loading of input voltage pads must not result in exceeding contact current limits. Each connector Vcc contact is rated for a maximum current of 1500 mA. Note 4: Plug Sequence specifies the mating sequence of the host connector and module. The sequence is 1, 2, and 3 see Figure 14 for pad locations.

5.2 QSFP112 Low Speed Electrical Hardware Signals ‌
In addition to the TWI serial interface the module has the following low speed signals for control and status:
 ModSelL
 ResetL
 LPMode/TxDis
 ModPrsL
 IntL/RxLOSL

9 The QSFP112 low speed is similar and follows SFF-8679 [32] specifications. 10

5.2.1 ModSelL ‌
The ModSelL is an input signal that shall be pulled to Vcc in the QSFP112 modules (see Table 16). When
held low by the host, the module responds to TWI serial communication commands. The ModSelL allows the
use of multiple QSFP112 modules on a single TWI interface bus. When ModSelL is “High”, the module shall
not respond to or acknowledge any TWI interface communication from the host. 16

In order to avoid conflicts, the host system shall not attempt TWI interface communications within the ModSelL
de-assert time after any QSFP112modules are deselected. Similarly, the host must wait at least for the period
of the ModSelL assert time before communicating with the newly selected module. The assertion and de-
asserting periods of different modules may overlap as long as the above timing requirements are met. 21

5.2.2 ResetL ‌
The ResetL signal shall be pulled to Vcc in the module (see Table 16). A low level on the ResetL signal for
longer than the minimum pulse length (t_Reset_init) (See Table 18) initiates a complete module reset,
returning all user module settings to their default state. 26

5.2.3 LPMode/TxDis ‌
LPMode/TxDis is a dual-mode input signal from the host operating with active high logic. It shall be pulled
towards Vcc in the module. At power-up or after ResetL is deasserted LPMode/TxDis behaves as LPMode. If
supported, LPMode/TxDis can be configured as TxDis using the TWI interface except during the execution of a
reset. Timing requirements for LPMode/TxDis mode changes are found in, see Table 18. LPMode is used in
the control of the module power mode, see CMIS [5] Chapter 6.3.1.3. 33

When LPMode/TxDis is configured as LPMode, the module behaves as though TxDis=0. By using the
LPMode signal and a combination of the Power_override, Power_set and High_Power_Class_Enable software
control bits the host controls how much power a module can consume. When LPMode/TxDis is configured as
TxDis, the module behaves as though LPMode=0. In this mode LPMode/TxDis when set to 1 or 0 disables or
enables all optical transmitters within the times specified in Table 18. 39

Changing LPMode/TxDis mode from LPMode to TxDis when the LPMode/TxDis state is high disables all
optical transmitters. If the module was in low power mode, then the module transitions out of low power mode
at the same time. If the module is already in high power state (Power Override control bits) with transmitters
already enabled, the module shall disable all optical transmitters. Changing the LPMode/TxDis mode from
LPMode to TxDis when the LPMode/TxDis state is low, simply changes the behavior of the mode of
LPMode/TxDis. The behavior of the module depends on the Power Override control bits. 46

Note that the “soft” functions of TxDis, LPMode, IntL and RxLOSL allow the host to poll or set these values
over the TWI interface as an alternative to monitoring/setting signal values. Asserting either the “hardware” or
“soft bit” (or both) for TxDis or LPMode results in that function being asserted. 50

Editor’s Note: registers to support optional TxDis will be added in future revisions of CMIS.
2
1. 5.2.4 ModPrsL ‌
2. ModPrsL shall be pulled up to Vcc Host on the host board and pulled low in the module (see Table 16). The
3. ModPrsL is asserted “Low” when the module is inserted. The ModPrsL is deasserted “High” when the module
4. is physically absent from the host connector due to the pull-up resistor on the host board. 7
1. 5.2.5 IntL/RxLOSL ‌
2. IntL/RxLOSL is a dual-mode active-low, open-collector output signal from the module. It shall be pulled up
3. towards Vcc on the host board (see Table 16). At power-up or after ResetL is released to high, IntL/RxLOSL is
4. configured as IntL. When the IntL signal is asserted Low it indicates a change in module state, a possible
5. module operational fault or a status critical to the host system. The host identifies the source of the interrupt
6. using the TWI serial interface. The IntL signal is deasserted “High” after all set interrupt flags are read. If dual
7. mode operation supported, IntL/RxLOSL can be optionally programmed as RxLOSL using the TWI interface
8. except during the execution of a reset. If the module has no interrupt flags asserted (IntL/RxLOSL is high),
9. there should be no change in IntL/RxLOSL states after the mode change. 17
1. If IntL/RxLOSL is configured as RxLOSL, a low indicates that there is a loss of received optical power on at
2. least one lane. “high” indicates that there is no loss of received optical power. Timing requirements for
3. IntL/RxLOSL including fast RxLOS mode are found in Table 18. The actual condition of loss of optical receive
4. power is specified by other governing documents, as the alarm threshold level is application specific. The
5. module shall pull RxLOSL to low if any lane in a multiple lane module or cable has a LOS condition and shall
6. release RxLOSL to high only if no lane has a LOS condition. 24
25 Editor’s note registers to support optional RxLOSL will be added in future revisions of CMIS.
26
1. 5.3 Examples of QSFP112 Host Board Schematic ‌
2. Figure 15, Figure 16, and Figure 17 show examples of QSFP112 host PCB schematics with connections to
3. CDR and control ICs. A 4-wide electrical/optical interface is shown. Note alternate electrical/optical interfaces
4. are supported using optical multiplexing (WDM) or electrical multiplexing. The QSFP112 host board
5. schematics are similar to SFF-8679 [32] but follows QSFP-DD/QSFP-DD800 schematics, with specifics pullup
6. resistors listed on the schematics. 33
Note: Filter capacitors values are informative and application dependent,
0.1 F capacitors should be placed in close proximity to power pads and may be duplicated for individual pads to provide additional high frequency filtering.

Note: Vcc1 may be connected to VccTx or VccRx within the module provided the applicable derating of the maximum current limit is used.

1
Figure 15: Example QSFP112 Host Board Schematic for Optical Modules

Note: Vcc1 may be connected to VccTx or VccRx within the module provided the applicable derating of the maximum current limit is used.

2 Figure 16: Example QSFP112 host board schematic for Active Copper Cable Module

Note: Recommended filtering is only valid for dedicated passive copper cable ports. For ports supporting both passive and active modules use recommended filtering from Figure 16 or 17.

2 Figure 17: Example QSFP112 Host Board Schematic for Passive Copper Cable Module

5.4 Low Speed Electrical Specification ‌
TWI bus composed of the initiator and the target devices, the initiator controls the bus and the target device
respond to the initiator requests. This section follows QSFP-DD/QSFP-DD800 4.4 TWI logics levels and bus
loading. This specification follows SFF-8679 [32] but with following exceptions, supporting 1 MHz FastMode+
and different Iin.
5.4.1 TWI Logic Levels and Bus Loading ‌
Low speed signaling other than the SCL and SDA interface is based on Low Voltage (LVTTL/LVCMOS)
operating at Vcc. Vcc refers to the generic supply voltages of VccTx, VccRx, Vcc host or Vcc1. Hosts shall
use a pull-up resistor connected to Vcc host on each of the TWI interface SCL (clock), SDA (data), and all low
speed status outputs (see Table 16). The SCL and SDA is a hot plug interface that may support a bus
topology. During module insertion or removal, the module may implement a pre-charge circuit which prevents
corrupting data transfers from other modules that are already using the bus. 13

Tradeoffs between pull-up resistor values, total bus capacitance and the estimated bus rise/fall times are
shown Figure 18.

The QSFP112 low speed electrical specifications are given in Table 16, where some of the parameters are
more stringent than JEDEC JESD8C [20]. Implementations compliant to this specification ensures
compatibility between TWI host bus initiator and the TWI target device. 20

21 Table 16- Low Speed Control and Sense Signals

Parameter	Symbol	Min	Max	Unit	Condition
SCL and SDA	VOL	0	0.4	V	IOL (max)=3 mA for fast mode, 20 mA for Fast-mode plus
SCL and SDA	VIL	-0.3	Vcc*0.3	V
SCL and SDA	VIH	Vcc*0.7	Vcc+0.5	V
Capacitance for SCL and SDA I/O signal	Ci		14	pF
Total bus capacitive load for SCL and SDA	Cb		100	pF	For 400 kHz clock rate use 3 k pullup resistor, max. For 1000 kHz clock rate refer to Figure 6.
Total bus capacitive load for SCL and SDA	Cb		200	pF	For 400 kHz clock rate use 1.6 k pullup resistor, max. For 1000 kHz clock rate refer to Figure 6.
LPMode/TxDis, ResetL, ModSelL	VIL	-0.3	0.8	V
LPMode/TxDis, ResetL, ModSelL	VIH	2	Vcc+0.3	V
LPMode, ResetL and ModSelL	\|Iin\|		360	A	0V<Vin<Vcc
IntL/RxLOS	VOL	0	0.4	V	IOL=2.0 mA
IntL/RxLOS	VOH	Vcc-0.5	Vcc+0.3	V	10 k pull-up to Host Vcc
ModPrsL	VOL	0	0.4	V	IOL=2.0 mA
ModPrsL	VOH				ModPrsL can be implemented as a short-circuit to GND on the module

Figure 18: SDA/SCL options for pull-up resistor, bus capacitance and rise/fall times

5.5 Management Interface ‌
A management interface, as already commonly used in other form factors like QSFP, SFP, and CDFP, is
specified in order to enable flexible use of the module by the user. The QSFP-DD/QSFP-DD800, and
QSFP112 modules memory map are based on “Common Management Interface Specification (CMIS)” (see
www.QSFP-DD.com) [5]. Note: The CMIS management memory map structurally supports multiples of
8 lanes. In case of QSFP112 plugged into QSFP-DD/QSFP-DD800 or into QSFP112 socket, host lanes 5-8
are physically not connected and should be ignored. This is visible to a host by the fact that all of the
QSFP112 advertised data paths for module Applications make use of host lanes 1-4 only. 12

Some timing requirements are critical, especially for a multi-lane device, so the interface speed may optionally
be increased. Byte 00h on the Lower Page or Address 128 Page 00h is used to indicate the use of CMIS with
4 host lanes instead of 8 lanes. When a classic QSFP+/QSFP28 module is inserted into a QSFP112 port the
host must determine which memory map to use (e.g., SFF-8636 [30] or CMIS [5]) based on the QSFP+
identifier at Byte 00h on the Lower Page or Address 128 Page 00h. 18

In some applications, muxing or demuxing may occur in the module. In this specification, all references to lane
numbers are based on the electrical connector interface lanes, unless otherwise indicated. In cases where a
status or control aspect is applicable only to lanes after muxing or demuxing has occurred, the status or control
is intended to apply to all lanes in the mux group, unless otherwise indicated. 23

Low speed signaling is based on Low Voltage CMOS (LVCMOS) operating at Vcc, [20]. Hosts shall use a pull-
up resistor connected to Vcc_host on the TWI interface SCL (clock) and SDA (Data) signals. Detailed electrical
specifications are given in 5.4. Timing specifications for management functionality involving electrical low
speed signals are found are given in Table 18 28

29 Nomenclature for all registers more than 1 bit long is MSB-LSB. 30

5.5.1 Management Interface Timing Specification ‌
The timing parameters for the TWI interface (TWI) to the QSFP112 module memory transaction timings are
shown in Figure 19 and specified in Table 17 and is compatible with I2C [21]. The default clock rate is a
maximum of 400 kHz with an option to support up to a maximum of 1 MHz. This clause closely follows the
QSFP+ SFF-8636 [30] specification but with the addition of Fast Mode+. This specification also defines tBUF
timing, tWR timing, tNACK timing, tBPC timing. 8

11 Figure 19: TWI Timing Diagram

1 Table 17- Management Interface timing parameters

TWI Modes		Fast Mode (400 kHz)		Fast Mode+ (1 MHz)
Parameter	Symbol	Min	Max	Min	Max	Unit	Conditions
Clock Frequency	fSCL	0	400	0	1000	kHz
Clock Pulse Width Low	tLOW	1.3		0.50		µs
Clock Pulse Width High	tHIGH	0.6		0.26		µs
Time bus free before new transmission can start	tBUF	20		20		µs	Between STOP and START and between ACK and ReStart
START Hold Time	tHD.STA	0.6		0.26		µs	The delay required between SDA becoming low and SCL starting to go low in a START
START Setup Time	tSU.STA	0.6		0.26		µs	The delay required between SCL becoming high and SDA starting to go low in a START
Data In Hold Time	tHD.DAT	0		0		µs
Data In Setup Time	tSU.DAT	0.1		0.1		µs
Input Rise Time	tR		300		120	ns	From (VL,MAX=0.3Vcc) to (VIH,MIN=0.7Vcc), see Figure 6
Input Fall Time	tF		300		120	ns	From (VIH,MIN=0.7Vcc) to (VIL,MAX=0.3Vcc), see Figure 6
STOP Setup Time	tSU.STO	0.6		0.26		µs
STOP Hold Time	tHD.STO	0.6		0.26		µs
Aborted sequence – bus release	Deselect _Abort		2		2	ms	Delay from a host de-asserting ModSelL (at any point in a bus sequence) to the QSFP-DD module releasing SCL and SDA
ModSelL Setup Time1	tSU. ModSelL	2		2		ms	ModSelL Setup Time is the setup time on the select line before the start of a host initiated TWI serial bus sequence.
ModSelL Hold Time1	tHD. ModSelL	2		2		ms	ModSelL Hold Time is the delay from completion of TWI serial bus sequence to changes of module select status.
TWI Serial Interface Clock Holdoff “Clock Stretching”	T_clock_ hold		500		500	µs	Time the QSFP-DD module may hold the SCL line low before continuing with a read or write operation.
Complete Single or Sequential Write to non- volatile registers	tWR		80		80	ms	Time to complete a Single or Sequential Write to non-volatile registers.
Accept a single or sequential write to volatile memory	tNACK		10		10	ms	Time to complete a Single or Sequential Write to volatile registers.
Time to complete a memory bank/page	tBPC		10		10	ms	Time to complete a memory bank and/or page change.
Endurance (Write Cycles)		50k		50k		cycles	Module Case Temperature = 70 ºC
Note 1: Management registers can be read to determine alternate ModSelL set up and hold times. See CMIS 8.4.5, Durations Advertising or SFF-8636 6.2.9, Free Side Device Properties (Page 00h, Bytes 107-115).

The TWI serial interface address of the QSFP112 module is 1010000X (A0h). In order to allow access to
multiple QSFP-DD/QSFP-DD800 modules on the same TWI serial bus, the QSFP112 includes a module select
pad, ModSelL. This input (which is pulled high, deselected in the module) must be held low by the host to
select the module of interest and allow communication over the TWI serial interface. The module must not
respond to or accept TWI serial bus instructions unless it is selected. 6

Before initiating a TWI serial bus communication, the host shall provide setup time on the ModSelL line of all
modules on the TWI bus. The host shall not change the ModSelL line of any module until the TWI serial bus
communication is complete and the hold time requirement is satisfied. 10

5.5.1.1 Bus timing tBUF
The timing attribute tBUF is the bus free time between sequential TWI transactions, see Figure 20. It’s
measured from the low to high SDA edge of the Stop condition of the Write transaction to the high to low SDA
edge of the Start condition for the next transaction. 15
1. 5.5.1.2 Bus timing tWR
2. The timing attribute tWR is the maximum time allowed for a module to complete its internally timed write cycle
3. after a single or sequential write to non-volatile memory before the next basic management operation can be
4. accepted, see Figure 20. The write cycle completion time is measured from the low to high SDA edge of the
5. STOP condition of the Write transaction to the high to low SDA edge of the START condition for the next
6. transaction.
22

23
24
25 Figure 20: Bus timing tWR

12

5.5.1.3 Bus timing tNACK
The timing attribute tNACK is the maximum time allowed for a module to complete its internally timed write
cycle after a single or sequential write to a volatile memory location before the next basic management
operation can be accepted, see Figure 21. The write cycle completion time is measured from the low to high
SDA edge of the STOP condition of the Write transaction to the high to low SDA edge of the START condition
for the next transaction. 9

11 Figure 21: Bus timing tNACK

5.5.1.4 Bus timing tBPC
The timing attribute tBPC is the time required for a module to complete the change for the requested Bank
and/or Page selection, see Figure 22. It’s measured from the low to high SDA edge of the Stop condition of
the Write transaction to the high to low SDA edge of the Start condition for the next transaction.

2 Figure 22: Bus timing tBPC

5.5.2 Timing for soft control and status functions ‌
Timing for QSFP112 soft control status functions is described in Table 18. Squelch and disable timings are
defined in Table 19.

Table 18- Timing for QSFP112 soft control and status functions

Parameter	Symbol	Min	Max	Unit	Conditions
MgmtInitDuration	Max MgmtInit Duration		2000	ms	Time from power on1, hot plug or rising edge of reset until until the high to low SDA transition of the Start condition for the first acknowledged TWI transaction.
ResetL Assert Time	t_reset_init	10		µs	Minimum pulse time on the ResetL signal to initiate a module reset.
Int/RxLOS Mode Change	t_IntL/RxLOSL		100	ms	Time to change between IntL and RxLOSL modes of the dual- mode signal IntL/RxLOSL.
LPMode/TxDis mode change time	t_LPMode/TxDis		100	ms	Time to change between LPMode and TxDis modes of LPMode/TxDis
IntL Assert Time	ton_IntL		200	ms	Time from occurrence of condition triggering IntL until Vout:IntL=Vol
IntL Deassert Time	toff_IntL		500	µs	Time from clear on read2 operation of associated flag until Vout:IntL=Voh. This includes deassert times for Rx LOS, Tx Fault and other flag bits.
RxLOS Assert Time	ton_los		100	ms	Time from Rx LOS condition present to Rx LOS bit set (value = 1b) and IntL asserted 3.
Rx LOS Assert Time (optional fast mode)	ton_losf		1	ms	Time from Rx LOS state to Rx LOS bit set (value = 1b) and IntL asserted 3.
RxLOS Deassert Time (optional fast mode)	toff_f_LOS		3	ms	Optional fast mode is advertised via the CMIS. Time from optical signal above the LOS deassert threshold to when the module releases the RxLOSL signal to high.
TX Disable Assert Time	ton_TxDis		100	ms	Time from Tx Disable bit set to 1 until optical output falls below 10% of nominal.
TX Disable Assert Time (optional fast mode)	ton_f_TxDis		3	ms	Optional fast mode is advertised via CMIS. Time from TxDis signal high to the optical output reaching the disabled level
TX Disable Deassert Time	toff_TxDis		400	ms	Time from Tx Disable bit cleared to 1 until optical output rises above 90% of nominal 4.
Tx Fault Assert Time	ton_Txfault		200	ms	Time from Tx Fault state to Tx Fault bit set (value=1b) and IntL asserted.
Flag Assert Time	ton_flag		200	ms	Time from occurrence of condition triggering flag to associated flag bit set (value=1b) and IntL asserted.
Mask Assert Time	ton_mask		100	ms	Time from mask bit set (value=1b) 5 until associated IntL assertion is inhibited
Mask Deassert Time	toff_mask		100	ms	Time from mask bit cleared (value=0b) 5 until associated IntL operation resumes
Data Path Tx Turn On Max Duration6	DataPathTxTurnOn_MaxDuration				see CMIS memory P01h: B168
Data Path Tx Turn Off Max Duration6	DataPathTxTurnOff_MaxDuration				see CMIS memory P01h: B168
Data Path Deinit Max Duration6	DataPathDeinit_MaxDuration				see CMIS memory P01h: B144

Data Path Init Max Duration6	DataPathInit_MaxDuration	see CMIS memory P01h: B144
Module Pwr Up Max Duration7	ModulePwrUp_MaxDuration	see CMIS memory P01h: B167
Module Pwr Dn Max Duration7	ModulePwrDn_MaxDuration	see CMIS memory P01h: B167
Notes: 1. Power on is defined as the instant when supply voltages reach and remain at or above the minimum level specified in Table 21.
Measured from low to high SDA edge of the Stop condition of the read transaction. Rx LOS condition is defined at the optical input by the relevant standard. Tx Squelch Deassert time is longer than SFF-8679 [32].
5. Measured from low to high SDA edge of the Stop condition of the write transaction.
Measured from the low to high SDA edge of the Stop condition of the Write transaction until the IntL for the state change Vout:IntL=Vol, unless the module advertises a less than 1 ms duration in which case there is no defined measurement. Measured from the low to high SDA edge of the Stop condition of the Write transaction until the IntL for the state change Vout:IntL=Vol.

Table 19- I/O Timing for Squelch & Disable

Parameter	Symbol	Max	Unit	Conditions
Rx Squelch Assert Time	ton_Rxsq	15	ms	Time from loss of Rx input signal until the squelched output condition is reached, see 4.6.1.
Tx Squelch Assert Time	ton_Txsq	400	ms	Time from loss of Tx input signal until the squelched output condition is reached, see 4.6.2.
Tx Squelch Deassert Time	toff_Txsq	1.5	s	Tx squelch deassert is system and implementation dependent, see also 4.6.2.
Tx Disable Assert Time	ton_txdis	100	ms	Time from the stop condition of the Tx Disable write sequence1 until optical output falls below 10% of nominal.
Tx Disable Assert Time (optional fast mode)	ton_txdisf	3	ms	Time from Tx Disable bit set (value = 1b)1 until optical output falls below 10% of nominal, see notes 2 and 3.
Tx Disable Deassert Time	toff_txdis	400	ms	Time from Tx Disable bit cleared (value = 0b)1 until optical output rises above 90% of nominal, see notes 2, and 3.
Tx Disable Deassert Time (optional fast mode)	toff_txdisf	10	ms	Time from Tx Disable bit cleared (value = 0b)1 until optical output rises above 90% of nominal, see notes 2 and 3.
Rx Output Disable Assert Time	ton_rxdis	100	ms	Time from Rx Output Disable bit set (value = 1b)1 until Rx output falls below 10% of nominal
Rx Output Disable Deassert Time	toff_rxdis	100	ms	Time from Rx Output Disable bit cleared (value = 0b)1 until Rx output rises above 90% of nominal.
Squelch Disable Assert Time	ton_sqdis	100	ms	This applies to Rx and Tx Squelch and is the time from bit set (value = 0b)1 until squelch functionality is disabled.
Squelch Disable Deassert Time	toff_sqdis	100	ms	This applies to Rx and Tx Squelch and is the time from bit cleared (value = 0b)1 until squelch functionality is enabled.
Notes: Measured from LOW to HIGH SDA signal transition of the STOP condition of the write transaction. CMIS 4.0 and beyond the listed values are superseded by the advertised DataPathTxTurnOff_MaxDuration and DataPathTxTurnOn_MaxDuration times in P01h.168. Listed values place a limit on the DataPathTxTurnOff_MaxDuration and DataPathTxTurnOn_MaxDuration times (P01h.168) that can be advertised by such modules (for CMIS 4.0 and beyond).

5.6 High Speed Electrical Specification ‌
For detailed QSFP112 electrical specifications for operation up to 29 GBd see e.g., IEEE Std 802.3-2018
Annex 86A, Annex 83E, Annex 120C, or Annex 120E [15]; Fibre Channel FC-PI-6 [1], FC-PI-7 [2]; OIF CEI 4.0
[22]; InfiniBand FDR, EDR, and HDR specifications [19]. For detailed QSFP-DD-800 electrical specifications
for operation up to 58 GBd see e.g., IEEE P802.3ck Annex 120G [17]; Fibre Channel FC-PI-8 [3]; OIF CEI-
112G-VSR [22]; InfiniBand NDR specifications [19].

Partial or complete squelch specifications may be provided in the appropriate specification. Where squelch is
not fully defined by the appropriate specification, the recommendations of the following subsections 5.6.1 and
5.6.2 may be used.

12 Editor’s note: squelch levels for 100 Gb/s PAM4 may need to be lowered and currently under investigation.

14 5.6.1 Rx(n)(p/n)‌

Rx(n)(p/n) are QSFP112 module receiver data outputs. Rx(n)(p/n) are AC-coupled 100 Ohm differential lines
that should be terminated with 100 Ohm differentially at the Host ASIC(SerDes). The AC coupling is inside the
QSFP112 modules and not required on the Host board. When properly terminated, the differential voltage
swing shall be less than or equal to 900 mVpp or as defined by the relevant standard, or whichever is less. 19

Output squelch for loss of optical input signal, hereafter Rx Squelch, is required and shall function as follows.
In the event of the Rx input signal on any optical port becoming equal to or less than the level required to
assert LOS, then the receiver output(s) associated with that Rx port shall be squelched. A single Rx optical
port can be associated with more than one Rx output as shown in Table 24. In the squelched state output
impedance levels are maintained while the differential voltage amplitude shall be less than 50 mVpp. 25

In normal operation the default case has Rx Squelch active. Rx Squelch can be deactivated using Rx Squelch
Disable through the TWI serial interface. Rx Squelch Disable is an optional function.
5.6.2 Tx(n)(p/n)‌
Tx(n)(p/n) are QSFP-DD module transmitter data inputs. They are AC-coupled 100 Ohm differential lines with
100 Ohm differential terminations inside the QSFP112 optical module. The AC coupling is implemented inside
the QSFP112 optical module and not required on the Host board. 32

Output squelch for loss of electrical signal, hereafter Tx Squelch, is an optional function. Where implemented it
shall function as follows. In the event of the differential, peak-to-peak electrical signal amplitude on any
electrical input lane becoming less than 70 mVpp, then the transmitter optical output associated with that
electrical input lane shall be squelched and the associated TxLOS flag set. If multiple electrical input lanes are
associated with the same optical output lanes, the loss of any of the incoming electrical input lanes causes the
optical output lane to be squelched. 39

For applications, e.g., Ethernet, where the transmitter off condition is defined in terms of average power,
squelching by disabling the transmitter is recommended and for applications, e.g., InfiniBand, where the
transmitter off condition is defined in terms of OMA, squelching the transmitter by setting the OMA to a low
level is recommended. 44

In module operation, where Tx Squelch is implemented, the default case has Tx Squelch active. Tx Squelch
can be deactivated using Tx Squelch Disable through the TWI serial interface. Tx Squelch and Tx Squelch
Disable are optional functions. 48

5.7 Power Requirements‌
The power supply has three designated pads, VccTx, Vcc1, and VccRx in the connector. VccRx, Vcc1, and
VccTx may be internally connected within the module in any combination at the discretion of the module
vendor. Power is applied concurrently to these pads. 5

A host board together with the QSFP112 module(s) forms an integrated power system. The host supplies
stable power to the module. The module limits electrical noise coupled back into the host system and limits
inrush charge/current during hot plug insertion or module state transitions. 9

All power supply requirements in Table 21 shall be met at the maximum power supply current. No power
sequencing of the power supply is required of the host system since the module sequences the contacts in the
order of ground, supply and signals during insertion. 13

5.7.1 QSFP112 Power Classes and Maximum Power Consumption ‌
There are two power modes: Low Power Mode and High Power Mode, and eight power classes, Class 1 -
Class 8. Module power classes are defined in Table 20 and module power specifications are provided in Table
21.

Since a wide range of module power classes exist, to avoid exceeding the system power supply limits and
cooling capacity when a module is inserted into a system designed to accommodate only low power
consumption modules, it is recommended that host systems designed to accommodate only low power
consumption modules also implement the state machine defined in the CMIS [5] and identify the power class of
the module before allowing the module to go into High Power Mode, where power class 8 requires reading
CMIS (Page00, Byte 201) to determine actual power consumption. This is to avoid exceeding the host system
power supply limits and cooling capacity when a module exceeding the power class supported by the system is
inserted.

28 Table 20- QSFP112 Power Classes

Power Class	Max Power (W)	CMIS Register
1	1.5	Direct readout of Page 00h Byte 200[000xxxxx]
2	2.0	Direct readout of Page 00h Byte 200[001xxxxx]
3	2.5	Direct readout of Page 00h Byte 200[010xxxxx]
4	3.5	Direct readout of Page 00h Byte 200[011xxxxx]
5	4.0	Direct readout of Page 00h Byte 200[100xxxxx]
6	4.5	Direct readout of Page 00h Byte 200[101xxxxx]
7	5.0	Direct readout of Page 00h Byte 200[110xxxxx]
8 1	>5.0	Direct readout of Page 00h Byte 200[111xxxxx]
Note: 1. When a module reports power class 8 the host must read CMIS Page 00h Byte 201 to determine module power dissipation. Please see CMIS Byte 201 register definition for more information.

In general, the higher power classification levels are associated with higher data rates and longer reaches. The
system designer is responsible for ensuring that the maximum case temperature does not exceed the case
temperature requirements.

5.7.2 QSFP112 Host Board Power Supply Filtering ‌
The specification of the host power supply filtering network is beyond the scope of this specification,
particularly because of the wide range of module Power Classes. During power transient events, the host
should ensure that any neighboring modules sharing the same supply stay within their specified supply voltage
limits. The host should also ensure that the intrinsic noise of the power rail is filtered to guarantee the correct
operation of the optical modules. The reference power supply filter is shown in Figure 23.

8 Figure 23: Reference Power Supply Filter for Module Testing

Any voltage drop across a filter network on the host is counted against the host DC set point accuracy
specification. System designers should choose components with appropriate DCR and ESR, in order to
minimize the voltage drop and the amount of noise coupled to the module. System designers should carefully
choose components with appropriate DCR and ESR on host supporting power class 6 or higher, in order to
minimize the voltage drop and the amount of noise coupled to the module. 15

The specifications for the power supply are shown in Table 21. The limits in Table 21 apply to the combined
current that flows through all inductors in the power supply filter (represents host Icc current Figure 23). Inrush
current shall be measured with the appropriate equipment, such as current probes or shunt resistors. The test
equipment shall provide enough bandwidth, vertical resolution, SNR and memory depth, in order to capture
properly all the power events. 21

5.7.3 Module Power Supply Specification ‌
To avoid exceeding the host system power capacity, if the host pulls LPMode low, the module upon hot-plug,
power cycle or reset proceed to High Power without host intervention. If the host does not pull LPMode high
the module will proceed to High Power Mode without host intervention. Figure 24 shows waveforms for
maximum instantaneous, sustained and steady state currents for Low Power and High Power modes.
Specification values for maximum instantaneous, sustained and steady state currents at each power class are
given in Table 21.

The module shall not be affected by the instantaneous variations of the power supply caused by its own
current drawing profile during all power transient events. The module shall support instantaneous power
supply Vcc variations with a slew rate up to 175 mV/ms. No traffic hits or TWI errors shall be observed during

Vcc variations.

Table 21- Power supply specifications, instantaneous, sustained, and steady state current limits

Parameter	Symbol	Min	Nom	Max	Unit
Power supply voltages VccTx, VccRx, and Vcc1 including ripple, droop and noise below 100 kHz1		3.135	3.3	3.465	V
Module inrush - instantaneous peak duration2	T_ip			50	µs
Module inrush - initialization time2	T_init			500	ms
Low Power Mode for all modules and Power Class 1 Module
Power Consumption Class	P_0			1.5	W
Instantaneous peak current at hot plug	Icc_ip_lp	-	-	600	mA
Sustained peak current at hot plug	Icc_sp_lp	-	-	495	mA
Steady state current	Icc_lp	See Note 3			mA
High Power Mode Power Class 2 module
Power Consumption Class	P_2			2.0	W
Instantaneous peak current	Icc_ip_2	-	-	800	mA
Sustained peak current	Icc_sp_2	-	-	660	mA
Steady state current	Icc_2	See Note 3			mA
High Power Mode Power Class 3 module
Power Consumption Class	P_3			2.5	W
Instantaneous peak current	Icc_ip_3	-	-	1000	mA
Sustained peak current	Icc_sp_3	-	-	825	mA
Steady state current	Icc_3	See Note 3			mA
High Power Mode Power Class 4 module
Power Consumption Class	P_4			3.5	W
Instantaneous peak current	Icc_ip_4	-	-	1400	mA
Sustained peak current	Icc_sp_4	-	-	1155	mA
Steady state current	Icc_4	See Note 3			mA
High Power Mode Power Class 5 module
Power Consumption Class	P_5			4.0	W
Instantaneous peak current	Icc_ip_5	-	-	1600	mA
Sustained peak current	Icc_sp_5	-	-	1320	mA
Steady state current	Icc_5	See Note 3			mA
High Power Mode Power Class 6 module
Power Consumption Class	P_6			4.5	W
Instantaneous peak current	Icc_ip_6	-	-	1800	mA
Sustained peak current	Icc_sp_6	-	-	1485	mA
Steady state current	Icc_6	See Note 3			mA
High Power Mode Power Class 7 module
Power Consumption Class	P_7			5.0	W
Instantaneous peak current	Icc_ip_7	-	-	2000	mA
Sustained peak current	Icc_sp_7	-	-	1650	mA
Steady state current	Icc_7	See Note 3			mA
High Power Mode Power Class 8 module
Power Consumption Class	P_84			>5.0	W
Instantaneous peak current	Icc_ip_8	-	-	P_8/2.5	A
Sustained peak current	Icc_sp_8	-	-	P_8/3.03	A
Steady state current	Icc_8	-	-	4.5	A
Notes: 1. Measured at VccTx, VccRx, and Vcc1. 2: T_ip and T_init are test conditions for measuring inrush current and not characteristics of the module. 3: The module must stay within its declared power class. 4: P_8 is the module power dissipation reported by CMIS Byte 201.

Figure 24: Instantaneous and sustained peak currents for Icc Host (see Table 13)

5.7.4 Host Board Power Supply Noise Output ‌
The host shall generate an effective weighted integrated spectrum RMS noise less than the eN_Host value in
Table 14 when tested by the methods of SFF-8431 [29], D.17.1 with the following exceptions:
a. The truncated function equation with coefficients from Table 22.
b. The resistor shall draw the maximum rated current per contact.

c. The frequency response of the truncated function is illustrated in Figure 25.

Table 22- Truncated Filter Response Coefficients for Host Power Supply Noise Output

Frequency	a	b	c	d	e
10 Hz < f < 240.2 Hz	0	0	0	0	-0.1
240.2 Hz < f < 24.03 kHz	0.3784	-3.6045	12.694	-19.556	11.002
24.03 kHz < f < 360.4 kHz	-22.67038	430.392	-3053.779	9574.26	-11175.98
360.4 kHz < f < 12.6 MHz	3.692166	-91.467	838.80	-3400.38	5139.285
12.6 MHz < f < 24 MHz	0	0	0	0	-60

6 Figure 25: Truncated Transfer Response for Host Board Power Supply Noise Output measurement

5.7.5 Module Power Supply Noise Output ‌
The QSFP112 modules when plugged into a reference module compliance board shall generate noise less
than the value in Table 23 when tested by the methods of SFF-8431 [29], D.17.2. The module must pass
module power supply noise output test in all operating modes. This test ensures the module will not couple
excessive noise from inside the module back onto the host board. 13

The RMS module noise voltage output is defined in the frequency band from 10 Hz to 10 MHz. Module noise
shall be measured with an appropriate probing technique at the input stage of the Vcc PSU filtering network,
see Figure 26.

Figure 26: Module Noise Injection Point

5.7.6 Module Power Supply Noise Tolerance ‌
The QSFP112 modules shall meet all requirements and remain fully operational in the presence of a reference
noise waveform described in Table 23 superimposed on the DC voltage. The reference noise waveform
consists of triangular sweep of supply voltage Vcc PSU from 3.135 to 3.465 while a sinusoidal 1 kHz to 1 MHz
noise is added to Vcc PSU. This emulates the worst case noise the module must tolerate and be fully
operational. The reference noise shall be injected at the input stage of the Vcc PSU filtering network, see
Figure 26. An appropriate probing technique is required for noise characterization. 12

13 Table 23- Power Supply Output Noise and Tolerance Specifications

Parameter	Symbol	Min	Nom	Max	Unit
Host RMS noise output 40 Hz-10 MHz (eN_Host)				25	mV
Module RMS noise output 10 Hz - 10 MHz				30	mV
Module sinusoidal power supply noise tolerance 1 kHz - 1 MHz (p-p) 1	PSNRmod			66	mV
Vcc PSU triangular tolerance waveform amplitude (p-p) 2		3.135		3.465	V
Vcc PSU triangular tolerance waveform frequency (p-p)		0.001		1000	Hz
Notes:

Module sinusoidal power supply noise must be added to the Vcc PSU triangular waveform.
Assumes nominal Vcc PSU=3.3 V.

5.8 ESD ‌
Where ESD performance is not otherwise specified, e.g., in the Ethernet specification, the QSFP-DD/QSFP-
DD800 modules shall meet ESD requirements given in EN61000-4-2, criterion B test specification when
installed in a properly grounded cage and chassis. The units are subjected to 15 kV air discharges during
operation and 8 kV direct contact discharges to the case. All the QSFP-DD/QSFP-DD800 modules and host
pads including high speed signal pads shall withstand 1000 V electrostatic discharge based on Human Body
Model per JEDEC JS-001 [9 ][20] and IEC EN61000-4-2 [8].

5.9 Clocking Considerations ‌
5.9.1 Data Path Description ‌
Within a module, host electrical and module media lanes are grouped together into a logical concept called a
data path. A data path is intended to represent a group of lanes over which a block of data is distributed that
will be powered up or down and initialized together. Some examples include a 400GAUI-4 to 400GBASE-DR4
module implementation, where the data path would include four host electrical lanes and four module media
lanes, or a 100GAUI-2 to 100GBASE-FR module implementation, where the data path would include 2 host
electrical lanes and one module media lane. 9

5.9.2 TX Clocking Considerations ‌
Within a given Tx data path the host is responsible for ensuring that all electrical lanes delivered to the module
are frequency synchronous (sourced from the same clock domain). If a module supports multiple Tx data paths
running concurrently, the different Tx data paths can either all be in a single clock domain or separate clock
domains. The module advertises which of these two modes it supports via the management registers. 15

If the module supports multiple Tx data paths running concurrently in a single clock domain, the module shall
ensure that active Tx data paths continue to operate undisturbed even as other Tx data paths (and their
associated Tx input lanes) are enabled/disabled by the host. 19

5.9.3 Rx Clocking Considerations ‌
Within a given Rx data path all lanes received on the module media interface are required to be frequency
synchronous (sourced from the same clock domain). If a module supports multiple Rx data paths running
concurrently, the module shall allow the different Rx data paths to be asynchronous from each other (sourced
from separate clock domains). 25

6 Optical Port Mapping and Optical Interfaces ‌
6.1 Electrical data input/output to optical port mapping ‌
Table 24 defines the mapping for QSFP-DD/QSFP-DD800 electrical Tx data inputs and Rx data outputs to
optical ports combinations. Note that there is no defined mapping of electrical input/output to optical
wavelengths for WDM applications. The QSFP112 with 4 transmit lanes [Tx1-Tx4] and 4 receive lanes [Rx1-
Rx4] allows optical port mapping as shown in Table 24, but the Tx/Rx lanes 5-8 should be ignored. 7

8 Table 24- Electrical Signal to Optical Port Mapping

Electrical data input/output	Optical port mapping (see Figure 27)
	Duplex LC, CS, SN, or MDC	MPO-12, Dual (CS, SN, MDC, Duplex LC, or MPO-12)	MPO-12, Quad (SN or MDC)	MPO-12 (two row), MPO-16, or Dual MPO-12	MPO-12, SN, MDC (BiDi)
	1 TX fiber 1 RX fiber 1	2 TX fibers 2 RX fibers 1	4 TX fibers 4 RX fibers 1	8 TX fibers 8 RX fibers 1,3	8 Tx (Rx) fibers 2,3
Tx1	TX-1	TX-1	TX-1	TX-1	TR1
Tx2			TX-1	TX-2	RT1
Tx3			TX-2	TX-3	TR2
Tx4			TX-2	TX-4	RT2
Tx5		TX-2	TX-3	TX-5	TR3
Tx6			TX-3	TX-6	RT3
Tx7			TX-4	TX-7	TR4
Tx8			TX-4	TX-8	RT4
Rx1	RX-1	RX-1	RX-1	RX-1	RT1
Rx2			RX-1	RX-2	TR1
Rx3			RX-2	RX-3	RT2
Rx4			RX-2	RX-4	TR2
Rx5		RX-2	RX-3	RX-5	RT3
Rx6			RX-3	RX-6	TR3
Rx7			RX-4	RX-7	RT4
Rx8			RX-4	RX-8	TR4
Notes: TX-n or RX-n where n is the optical port number as defined Figure 27. TRn or RTn where n is the optical port number as defined Figure 27. Some QSFP-DD/QSFP-DD800 modules may require fewer CS, SN, or MDC connectors. In such cases, Port #1 is always the left-most port. Successive ports then follow sequentially from left-to-right as shown in Figure 27.

6.2 Optical Interfaces ‌
The recommended location and numbering of the optical ports for 14 Media Dependent Interfaces (MDI) are
shown in Figure 27. The transmit and receive optical lanes shall occupy the positions depicted in Figure 27
when looking into the MDI receptacle with the connector keyway feature on top. QSFP-DD/QSFP-DD800
optical MDI examples are shown for three male MPO receptacles (see Figure 28, Figure 29, and Figure 30) a
duplex LC (see Figure 31), a Dual CS connector (see Figure 32), a Quad SN receptacle (see Figure 33), a
Quad MDC receptacle (see Figure 34), a Dual SN receptacle (see Figure 35), and a Dual MDC receptacle (see
Figure 36), a Dual Duplex LC receptacle (see Figure 37), and a Dual MPO-12 receptacle (see Figure 40 ).

MPO-12

1

TX
2 3

4

RX
4 3 2

1

Note: The MPO 12, 2 row optical MDI is used for breakout applications and is not intended for structured cabling applications.
MPO-16

TX

R
1 2 3
4
5
6
7
8
8
7 6
5 4

1 2 3
TX
5 6
MPO-12

1
1
2
2
TX
RX
TX
RX
Dual CS Du

1
2
3
TX
TX
RX
RX
Quad SN

Dual SN

1
1
RX
TX
2
1
TX
RX
2
Dual Duplex LC

2
3

RX
1
2
3
4
5
6
7 TX
8
TX
4
3
2
1
8
7
6
5
RX
Dual MPO-12

1
2
3

4
5
1. Note: For some CS, SN, and MDC use cases, fewer connector ports may be needed. In these cases, Port 1 is
2. always the left-most port. Successive ports then follow sequentially from left-to-right as shown. Dual Duplex
3. LC and Dual MPO port shall be positioned belly to belly, and the optical connector keys shall be oriented
4. towards the side walls of module. 10
  1. Figure 27: Optical Media Dependent Interface port assignments
    12
    13
    
    1
    1. 6.2.1 MPO Optical Cable connections ‌
    2. The optical plug and receptacle for the MPO-12 one row connectors are specified in TIA-604-5 [25] and IEC
    3. 61754-7-1 [11], see Figure 28. The optical plug and receptacle for one row MPO-16 connectors are specified
    4. in TIA-604-18 [27] and IEC 61754-7-3 [13] and shown in Figure 29. The optical plug and receptacle for the
    5. MPO-24 two row connectors are specified in TIA-604-5 [25] and IEC 61754-7-2 [12] see Figure 30. Note: This
    6. specification uses the terms MPO-12 in place of the TIA term MPO and MPO-12 Two Row in place of the TIA
    7. term MPO Two Row. 9
5. Aligned keys are used to ensure alignment between the modules and the patchcords. The optical connector is
6. orientated such that the keying feature of the MPO receptacle is on the top. Note: Two alignment pins are
7. present in each receptacle. 13
14
15
16
17
Figure 28: MPO-12 One row optical patchcord and module receptacle

Figure 29: MPO-16 One row optical patchcord and module receptacle
4

1

2
3
Figure 30: MPO-12 Two row optical patchcord and module receptacle

6.2.2 Duplex LC Optical Cable connection ‌
The Duplex LC optical plug and module receptacle are specified in TIA-604-10 [25] and IEC 61754-20 [14],
and shown in Figure 31.

6 Figure 31: Duplex LC optical patchcord and module receptacle

6.2.3 Dual CS Optical Cable connection ‌
The Dual CS optical receptacle for a QSFP-DD/QSFP-DD800 modules are specified in CS-01242017 [6] and
shown in Figure 32.
11

12

13
14 Figure 32: Dual CS connector optical patchcord and module receptacle
15

1
1. 6.2.4 Quad SN Optical Cable connections ‌
2. The Quad SN optical connector and receptacle for QSFP-DD/QSFP-DD800 module is specified in SN-
3. 60092019 [23] and shown in Figure 33. The top key and offset bottom key are used to ensure alignment
4. between the modules and the patch cords. 6
7
8
6.2.5 Quad MDC Optical Cable connection ‌
The Quad MDC optical plug and receptacle for a QSFP-DD/QSFP-DD800 modules are specified in USC-
11383001 [28] and shown in Figure 34. The optical connector is orientated such that the keying feature of the
MDC receptacle is on the top. 15

18 Figure 34: Quad MDC optical connector patchcord and four-port module receptacle

6.2.6 Dual SN Optical Cable connections ‌
The Dual SN optical connector and receptacle for QSFP-DD/QSFP-DD800 modules are specified in SN-
60092019 [23] and shown in Figure 35. The top key and offset bottom key are used to ensure alignment
between the modules and the patch cords. 5

8 Figure 35: Dual SN optical connector patchcord and dual-port module receptacle

6.2.7 Dual MDC Optical Cable connection ‌
The Dual MDC optical plug and receptacle for a QSFP-DD/QSFP-DD800 modules are specified in USC-
11383001 [28] and shown in Figure 36. The optical connector is orientated such that the keying feature of the
MDC receptacle is on the top. 15

18 Figure 36: Dual MDC optical connector patchcord and dual-port module receptacle

6.2.8 Dual Duplex LC Optical Cable connection ‌
The Dual Duplex LC module receptacle for a QSFP-DD Type 2B Module is shown in Figure 38. Each LC
Duplex interface is specified in TIA-605-10 [26], and the two LC Duplex ports need to be pitched at least 7.3
mm apart (Figure 43). The latches of LC plug may exceed the overall module width (see Figure 39). The pitch
between the cages in a system design will need to accommodate this excess width but it is not expected that
this will reduce port counts in a system. 7

Figure 37: Dual Duplex LC module receptacle (in support of breakout applications)
11

12
13
14 Figure 38: Dual Duplex LC module receptacle port pitch
15

16
17 Figure 39: Dual Duplex LC latch width

1

2 6.2.9 Dual MPO-12 Optical Cable connection‌
3 The Dual MPO-12 module receptacle for a QSFP-DD Type 2B module is shown in Figure 40. Each MPO-12
4 interface is specified in TIA-604-5 [25], and the two MPO-12 ports need to be pitched at least 10.2 mm apart
5 (Figure 41).’
6
7
8
9 Figure 40: Dual MPO module receptacle (in support of breakout applications)
10
11
12

13
14 Figure 41: Dual MPO-12 module receptacle port pitch
15
16
17
18
19
20
21
1. 6.3 Module Color Coding and Labeling ‌
2. An exposed feature of the QSFP-DD/QSFP-DD800 module (a feature or surface extending outside of the
3. bezel) should be color coded as follows:
4
1. Beige for 850nm
2. Blue for 1310nm
3. White for 1550nm
4. Above color coding list is not exhaustive, other specifications may define additional color codes to supplement
5. or override above color coding as needed. 10
11

Each QSFP-DD/QSFP-DD800 module shall be clearly labeled. The complete labeling need not be visible when
the QSFP-DD/QSFP-DD800 module is installed. QSFP-DD recess bottom area is the recommended location
of the label, but the location of label for QSFP-DD800 is on the module nose surface. Labeling shall include: 15

Appropriate manufacturing and part number identification
Appropriate regulatory compliance labeling
A manufacturing traceability code 19

20 The label should also include clear specification of the external port characteristics such as: 21

Optical wavelength
Required fiber characteristics (i.e., MMF/SMF)
Operating data rate
Interface standards supported
Link length supported
Connector Type

If required to comply with 10.3, a label must be applied to the top external surface of the module case, warning
of high touch temperature. 31

32 The labeling shall not interfere with the mechanical, thermal or EMI features. 33

7 QSFP-DD Mechanical and Board Definition ‌
This chapter is the foundation for QSFP-DD, QSFP-DD800, and QSFP112 modules specifications. Below is
the list of relevant sections applicable to QSFP-DD800 and QSFP112 in addition to QSFP-DD:
- 7.1 Introduction to QSFP-DD/QSFP-DD800 Modules
- 7.2 Datums, Dimensions and Component Alignment
- 7.3 Module Form Factors for QSFP-DD/QSFP-DD800
- 7.4 Module Flatness and Roughness 7.1.
7.1 Introduction to QSFP-DD/QSFP-DD800 Modules ‌
The cages and modules defined in this chapter are illustrated in Figure 42 (2x1 stacked cage and module),
Figure 43 (press fit cage for surface mount connector), and Figure 44 (illustrate Type 1, Type 2, Type 2A, and
Type 2B pluggable modules). All pluggable modules and direct attach cable plugs (both Type 1 and Type 2)
must mate to the connectors and cages defined in this specification. The Type 2 module allows an additional
extension of the module outside of the cage to allow for flexibility in module design. A Type 2A or Type 2B
modules include a heat sink on the extension of the module outside the cage to provide enhanced thermal
performance. Modules heatsink and retention clip thermal designs are application specific and not specifically
defined by this specification. See Appendix B for informative recommendations on overall module length
including handle. See Appendix C for recommended QSFP-DD heatsink on module extension design for Type
2A and 2B modules, Type 2B modules are only for QSFP-DD800 operation. See Appendix D for alternate
QSFP-DD800 heatsink design for Type 2A module. 20

27 Figure 42: 2x1 stacked cage and module

2 Figure 43: Press fit cage for surface mount connector

Type 1 Module

Type 2

Module

Type 2A Module

Type 2B Module

11 Figure 44: Type 1, Type 2, Type 2A, and Type 2B pluggable modules

7.2 Datums, Dimensions and Component Alignment ‌
A listing of the QSFP-DD/QSFP-DD800 datums for the various components is contained in Table 25. The
alignments of some of the datums are noted. To reduce the complexity of the drawings, all dimensions are
considered centered unless otherwise specified. Dimensions and tolerancing conform to ASME Y14.5-2009

[4]. All dimensions are in millimeters. 6

7 Table 25- Datums

Datum1	Description
A	Host Board Top Surface
B	Inside surface of bezel
C	Distance between Connector terminal thru holes on host board3
D	Hard stop on module2
E	Width of module3
F	Height of module housing
G	Width of module pc board3
H	Leading edge of signal contact pads on module pc board
J	Top surface of module pc board
K	Host board thru hole #1 to accept connector guidepost2
L	Host board thru hole #2 to accept connector guidepost2
M	Width of bezel cut out3
P	Vertical Center line of internal surface of cage
S	Seating plane of cage on host board
T	Hard stop on cage2
AA	Connector slot width3
BB	Seating plane of connector on host board
DD	Top surface of module housing
EE	Centerline of module opening to locate paddle card Datum H
FF	Centerline of upper port cage height
GG	Centerline of lower port cage height
EE	Primary Datum hole for 2x1 Host PCB
Notes:

All dimensions are in mm.
Datums D and T are aligned when assembled (see Figure 45 and Figure 46).
Centerlines of datums AA, C, E, G, M are aligned on the same vertical plane.

3 Figure 45: 2X1 stacked press fit connector/cage datum descriptions

3 Figure 46: Surface mount connector/cage datum descriptions

7.3 Module Form Factors for QSFP-DD/QSFP-DD800 ‌
The mechanical outline for the Type 1 module is shown in Figure 47, the Type 2 module is shown in Figure 48,
the Type 2A module with nose heat sink is shown in Figure 49, and the Type 2B module with taller nose heat
sink is shown in Figure 50. The module shall provide a means to self-lock with either the 2x1 stacked cage or
SMT cage upon insertion. The module package dimensions are defined in Figure 52, Figure 53, and Figure
54. The dimensions that control the size of the module that extends outside of the cage are listed as maximum
dimensions per Note 4.

3 Figure 47: Type 1 module

7 Figure 48: Type 2 module

2 Figure 49: Type 2A Module

4 Figure 50: Type 2B module

6 Figure 50 Type 2B Module (Cannot be used in combination with the 2x1 Electrical Connector Mechanical in section 7.7

7 due to possible mechanical interference)

2 Figure 51: Type 2A Module with heat sink

3 Figure 52: Drawing of the QSFP-DD module

3 Figure 53: Drawing of QSFP-DD module end face

6 Figure 54: Detailed dimensions of the QSFP-DD module opening

7.4 Module Flatness and Roughness ‌
QSFP-DD/QSFP-DD800 module flatness and roughness are specified to improve module thermal
characteristics when used with a riding heat sink. Relaxed specifications are used for lower power modules to
reduce cost. The module flatness and roughness specifications apply to the specified heat sink contact area
for QSFP-DD by Figure 52 and Figure 53 and for QSFP-DD800 by Figure 73. Specifications for QSFP-
DD/QSFP-DD800 Module flatness and surface roughness are shown in Table 26 (see Figure 52 and Figure
73 note 11), and the QSFP112 Module flatness and surface roughness are shown in Figure 24. Flatness and
roughness specifications applies to both top and bottom surfaces of the modules. Power class 1Cu is
dedicated to passive copper cables with a more relaxed flatness of 0.15 mm. 10

11 Table 26- QSFP-DD/QSFP-DD800 Module flatness specifications

Power Class1	Module Flatness (mm)	Surface Roughness (Ra, µm)
1Cu2	0.15	1.6
1	0.075	1.6
2	0.075	1.6
3	0.075	1.6
4	0.075	1.6
5	0.050	0.8
6	0.050	0.8
7	0.050	0.8
8	0.050	0.8
QSFP-DD/QSFP-DD800 power classes are defined in Table 12. Power class 1Cu maximum power dissipation is the same as power class 1.

13 Table 27- QSFP112 Module flatness specifications

Power Class1	Module Flatness (mm)	Surface Roughness (Ra, µm)
1Cu2	0.15	1.6
1	0.075	1.6
2	0.075	1.6
3	0.075	1.6
4	0.075	1.6
5	0.075	1.6
6	0.075	1.6
7	0.075	1.6
8	0.050	0.8
QSFP112 power classes are defined in Table 20. Power class 1Cu maximum power dissipation is the same as power class 1.

15 To improve thermal performance, optional enhanced surface specifications are specified in Table 28. This is an

16 optional specification and does not override the required specifications in Table 26 and Table 27. 17

18 Table 28- Optional Enhanced Module flatness specifications

Power Class	Module Flatness (mm)	Surface Roughness (Ra, µm)
8	0.025	0.4

1 7.5 QSFP-DD module paddle card dimensions notes‌

2 Notes for module paddle cards drawings applies to Figure 55 and Figure 56. 3

2 Figure 55: Module paddle card dimensions‌

3 Figure 56: Detail module pad dimensions

7.6 Module Extraction and Retention Forces ‌
The normative requirements for QSFP-DD/QSFP-DD800 insertion forces, extraction forces and retention
forces are specified in Appendix A. The contact pad plating shall meet the requirements in 7.5. 8

7.7 QSFP-DD 2x1 Stacked Electrical Connector Mechanical ‌
Each of the QSFP-DD stacked connectors are a 76-contacts right angle connector. The integrated connector in
a 2x1 stacked cage is shown in Figure 57 with detailed drawings in Figure 58, Figure 59 and Figure 60.

Recommendations for the 2x1 stacked cage bezel opening are shown in Figure 61. Recommended host PCB
layout are shown in Figure 63 and Figure 64. 3

4
5 Figure 57: Integrated connector in the 2x1 stacked cage

6

1
2
Figure 58: 2x1 stacked cage

3 Figure 59: 2x1 stacked cage dimensions

3 Figure 60: Connector pads in 2x1 stacked cage as viewed from front

7 Figure 61: 2x1 Bezel Opening

7.7.1 QSFP-DD 2x1 Connector and Cage host PCB layout ‌
A typical host board mechanical layout for attaching the QSFP-DD 2x1 Connector and Cage system is shown
in Figure 62 and Figure 63. Location of the pattern on the host board is application specific. To achieve 56
Gbps (28 GBd) operation the pad dimensions and associated tolerance must be adhered to and attention paid
 Toward Bezel
to the host layout. 6

9 Figure 62: 2X1 host board connector contacts

3 Figure 63: 2X1 Host PCB layout

4 Figure 64: 2X1 Host PCB detail layout

DETAIL 5

7.8 QSFP-DD Surface Mount Electrical Connector Mechanical ‌
The QSFP-DD Connector is a 76-contact, right angle connector. The SMT connector in a 1xn cage is shown in
Figure 65 with detailed drawings in Figure 66 and Figure 67 and Figure 69. SMT connector view and
connector detail designs are shown in Figure 68 and Figure 69. Recommendations for the SMT cage bezel
opening are shown in Figure 70. 7

12 Figure 65: SMT connector in 1xn cage

15 Notes apply to SMT 1xN cage drawing, see Figure 65, Figure 66, and Figure 67. 16

3 Figure 66: SMT 1x1 cage overview

4 Figure 67: SMT 1x1 cage detail design

2 Figure 68: SMT 1x1 connector front and side views

3 Figure 69: SMT 1x1 connector detail design

5 Note: Contact Dimension Measured from Datum T 6

3 Figure 70: SMT 1x1 bezel opening

7.8.1 QSFP-DD Surface mount connector and cage host PCB layout ‌
A typical host board mechanical layout for attaching the QSFP-DD surface mount Connector and Cage System
is shown in Figure 71 and Figure 72. Location of the pattern on the host board is application specific. 4

5 To achieve 25-50 Gbps performance pad dimensions and associated tolerances must be adhered to and

6 attention paid to the host board layout. 7

8 Notes for host PCB requirements (see Figure 71):

13 Figure 71: SMT host PCB layout

3 Figure 72: SMT Connector and host PCB contact numbers

8 QSFP-DD800 Mechanical and Board Definition ‌
Some of the QSFP-DD800 module mechanical specifications are common with QSFP-DD, below are the list of
relevant sections applicable to QSFP-DD800:
- 7.1 Introduction to QSFP-DD/QSFP-DD800 Modules
- 7.2 Datums, Dimensions and Component Alignment
- 7.3 Module Form Factors for QSFP-DD/QSFP-DD800
- 7.4 Module Flatness and Roughness.
8.1 Introduction ‌
The module paddle card dimensions of the QSFP-DD800 have been improved to support 100 Gb/s PAM4 (up
to 56 GBd) serial data rates, see Section 8.3. 11

QSFP-DD800 supports multiple connector/cage form factors. QSFP-DD800 cages/connectors/modules are
compatible with QSFP-DD cages/connectors/modules, QSFP-DD cages/connectors also accepts QSFP family
of modules. Examples of QSFP-DD800 cages are:
 1x1 surface mount connector/cage
 2x1 surface mount connector/cage
 2x1 surface mount connector/cage with cabled high-speed host interconnects on the top connector/
upper port of the cage. 19

20 8.2 QSFP-DD800 module mechanical dimensions‌

21 For QSFP-DD800 modules the bottom surface of the module within the cage shall be flat without a

22 pocket. The options for the position of the label could include the bottom surface of the module that protrudes

23 outside the bezel of the cage or etched into the metal surface. Caution should be exercised that any etchings

24 do not affect thermal performance. Flatness and roughness specs as defined in 7.4 apply for both top and

25 bottom surfaces of QSFP-DD800 module, see Figure 73 and Figure 74.

4 Figure 73: QSFP-DD800 module dimensions

3 Figure 74: QSFP-DD800 module leading edge dimensions

2 Figure 75: Detailed dimensions of the module opening

8.3 QSFP-DD800 improved module paddle card dimensions ‌
The QSFP-DD800 module paddle card pad dimensions have been modified to support 100 Gb/s serial data
rates. See Figure 76 and Figure 77 for QSFP-DD800 module updated paddle card pad dimensions. All other
module dimensions, except for the pads, remain the same as the QSFP-DD Hardware Specification defined in
Chapter 7.

3 Figure 76: QSFP-DD800 Module paddle card dimensions

2 Figure 77: QSFP-DD800 detail module paddle card dimensions

8.4 QSFP-DD800 1x1 SMT connector/cage ‌
The 1x1 SMT connector/cage mechanical outline for QSFP-DD800 is the same as the QSFP-DD 1x1
connector/cage, see 7.8.
8.4.1 Surface mount connector and cage host PCB layout ‌
A typical host board mechanical layout for attaching the QSFP-DD surface mount Connector and Cage System
is shown in Figure 78. Location of the pattern on the host board is application specific. 7

8 To achieve 112 Gbps (56 GBd) operation the QSFP-DD800 pad dimensions and associated tolerances have

9 improved compare to QSFP-DD and one must adhere and pay attention to the host board layout. 10

11 Notes for host PCB requirements (see Figure 78):

15 Figure 78: Reduced pad SMT host PCB layout

8.5 2x1 Surface Mount Technology (SMT) Connector/Cage ‌
The QSFP-DD800 2x1 SMT connector/cage mechanical outline has similar dimensions as the QSFP-DD 2x1
press fit connector/cage, see 7.7.
8.5.1 2x1 SMT Connector/Cage System ‌
Each of the QSFP-DD800 stacked connectors are a 76-contacts right angle connector A typical host board
mechanical layout for attaching the QSFP-DD800 surface mount connector and cage system are shown in
Figure 79 and Figure 80. The QSFP-DD800 connector and cage supports multiple host PCB implementations,
see Figure 85 and Figure 86. Location of the pattern on the host board is application specific. 9

10 To achieve 112 Gbps (56 GBd) operation the QSFP-DD800 pad dimensions and associated tolerances have

11 improved compared to QSFP-DD and one must adhere and pay attention to the host board layout. 12

3 Figure 79: QSFP-DD800 2x1 SMT Stack Cage

3 Figure 80: QSFP-DD800 2x1 SMT cage dimensions

2 Figure 81: Connector pads in 2x1 SMT stacked cage as viewed from front

6 Figure 82: 2x1 SMT Bezel Opening

 Toward Bezel

2 Figure 83: 2x1 SMT Pads Labeling

8.5.2 2x1 SMT Connector and Cage host PCB layout ‌
Examples of host board layout implementations for attaching the QSFP-DD800 2x1 connector and cage
system implementation 1 is shown in Figure 85 and implementation 2 is shown in Figure 86. The detail host
PCB layout for QSFP-DD800 is shown in Figure 87. Location of the pattern on the host board is application
specific. To achieve 112 Gbps (56 GBd) operation pad dimensions and associated tolerance must be adhered
to and attention paid to the host layout.

7

8 Figure 84: QSFP-DD800 stacked SMT 2x1 connector
9
10

1
2 Notes for host PCB requirements (see Figure 85, Figure 86, and Figure 87): 3

4
5

6
Figure 85: 2x1 SMT Connector and Cage PCB Layout Implementation 1

2 Figure 86: 2x1 SMT Connector and Cage PCB Layout Implementation 2

2 Figure 87: Detail QSFP800 2x1 SMT connector host layout

9 QSFP112 Mechanical and Board Definition ‌
Some of the QSFP112 module mechanical specifications are common with QSFP-DD, below is the list of
relevant sections applicable to QSFP112:
- 7.2 Datums, Dimensions and Component Alignment
- 7.4 Module Flatness and Roughness.
9.1 Introduction ‌
The module paddle card dimensions of the QSFP112 have been improved to support 100 Gb/s PAM4 (up to
56 GBd) serial data rates compare to QSFP+/QSFP28 [31] and [32].

QSFP112 supports multiple connector/cage form factors. All combinations of cages/connectors defined in the
specification are backwards compatible to accept classic QSFP28 and QSFP+ modules. In addition,
QSFP112 modules are compatible with QSFP/28/QSFP+ hosts for operation at lower speed. Examples of
QSFP112 cages are:
 1x1 surface mount connector/cage
 2x1 surface mount connector/cage. 16

9.2 QSFP112 module mechanical dimensions ‌
QSFP112 modules mechanical dimension are identical to QSFP+/QSFP28 modules [31] and [32] unless
specified otherwise. A QSFP28/56 [32] Style A cage can be used with the QSFP112 connector. For
QSFP112 modules the bottom surface of the module within the cage shall be flat without a pocket. The
options for the position of the label could include the bottom surface of the module that protrudes outside the
bezel of the cage or etched into the metal surface. Caution should be exercised that any etchings do not affect
thermal performance.
9.3 QSFP112 improved module paddle card dimensions ‌
The QSFP112 module paddle card pad dimensions have been modified to support 100 Gb/s serial data rates.
See Figure 88 for QSFP112 module updated paddle card pad dimensions. All other module dimensions,
except for the pads, remain the same as the QSFP+/QSFP28 specifications. 28

Figure 88 shows QSFP112 module paddle card dimensions. The QSFP112 connector can be integrated into a
1x1 or 2x1 stacked configuration with 1 or 2 ports as illustrated by Figure 90 and Figure 94. 4
1. For EMI protection the signals from the host connector should be shut off when the QSFP112 modules are not
2. present. Standard board layout practices such as connections to Vcc and GND with vias, use of short and
3. equal-length differential signal lines are recommended. The chassis ground (case common) of the QSFP112
4. modules should be isolated from the module’s circuit ground, GND, to provide the equipment designer
5. flexibility regarding connections between external electromagnetic interference shields and circuit ground,
6. GND, of the module. 11
1
2 Figure 88: QSFP112 improved paddle card dimensions‌
3
9.4 QSFP112 1x1 surface mount connector/cage ‌
The QSFP112 Connector is a 38-contacts, right angle connector optimized for 112Gbps (56 GBd) operation
which is backward compatible with classic QSFP28 and QSFP+ connector/cage. 7

8 QSFP112 1x1 SMT connector cage overview and the detailed drawings are shown in Figure 89 and Figure 90.

9 QSFP112 SMT connector front and side view is shown in Figure 91. 10

2 Figure 89: QSFP112 SMT 1x1 cage overview

2 Figure 90: QSFP112 SMT 1x1 cage detail design

2 Figure 91: QSFP112 SMT 1x1 connector front and side views

9.4.1 QSFP112 SMT host PCB layout ‌
A typical host board mechanical layout for attaching the QSFP112 surface mount Connector PCB is shown in
Figure 92, and the alternate layout implementation shown in Figure 93. Alternatively, a QSFP28/56 [32] Style
A cage can be used with the QSFP112 connector by combining the QSFP112 connector footprint with the
QSFP28/56 cage footprint as shown in Figure 93. 9

10 To achieve 112 Gbps (56 GBd) operation the QSFP112 pad dimensions and associated tolerances have

11 improved compare to QSFP28/QSFP+ and one must adhere and pay attention to the host board layout. 12

3 Notes for host PCB requirements (see Figure 92):

8 Figure 92: 1x1 SMT connector PCB layout implementation

0 .05

L-K

0 .05

3 .1

Ø 1 .55 ±0 .05

(2 .4 )

9 .0

7 .6

3 .4

9 .5

7 .4

0 .2

DATUM C

0 .2

7 .0

7 .6

9 .0

Ø 1 .05 ±0 .05 P TH (12 X)

7 .93

NO TE : THIS AR EA MUS T BE DE S IG NE D TO AVO ID ANY TR AC E S O R C O MP O NE NTS TO UC HING THE BO TTO M O F THE

C AG E O R C O NNE C TO R 2

Ø 1 .55 ±0 .05

3 .1

19 .0

16 .8

10 .6

2 .93

1 .93

37 .0

3 Figure 93: Alternate QSFP112 1x1 SMT connector PCB layout with QSFP28 Style A Cage

9.5 QSFP112 2x1 Stacked Surface Mount Connector/Cage ‌
Each of the stacked QSFP112 SMT connectors have 38-contacts. The QSFP112 is a right-angle connector
optimized for 112Gb/s (58 GBd) operation which is backward compatible with classic QSFP28 and QSFP+
connector/cage.

The QSFP112 2x1 SMT cage overview is shown in Figure 94. Location of the pattern on the host board is
application specific. The QSFP112 2x1 connector pinout as viewed from cage opening is shown in Figure 96,
QSFP112 2x1 connector pinout is shown in Figure 97, QSFP112 2x1 bezel opening is shown in Figure 98, and
QSFP112 2x1 SMT host pads labels are shown in Figure 99.

10
11
12
13

1
2 Figure 94: QSFP112 2x1 SMT Connector and Cage System
3

1
2 Figure 95: QSFP112 2x1 SMT Connector and Cage Detail View
3

1
2 Figure 96: QSFP112 2x1 stacked SMT connector
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

1

2
3 Figure 97: Connector pads in 2x1 SMT stacked cage as viewed from front
4

5
6 Figure 98: 2x1 SMT Bezel Opening
7

 Toward Bezel
1
2 Figure 99: 2x1 SMT host pads labeling
3
4
1. 9.5.1 QSFP112 2x1 SMT host PCB layout ‌
2. Examples of host board layout implementations for attaching the QSFP112 2x1 detail host PCB layout for
3. implementation 1 is shown in Figure 100 and for implementation 2 shown in Figure 101. Location of the
4. pattern on the host board is application specific. 9
To achieve 112 Gbps (56 GBd) operation the QSFP112 pad dimensions and associated tolerances have
improved compared to QSFP28/QSFP+ and one must adhere and pay attention to the host board layout. 12

13 Host PCB requirements notes:

3 Figure 100: QSFP112 2x1 SMT connector host layout implementation 1

4 Figure 101: QSFP112 2x1 SMT connector host layout implementation 2

10 Module Environmental and Thermal Requirements ‌
QSFP-DD/QSFP-DD800 modules are designed to allow for up to 36 modules; stacked, ganged and/or belly-to-
belly in a 1U 19" rack, with the appropriate thermal design for cooling/airflow. 4

The equipment supplier is responsible for controlling the module case temperature to the specified range. The
module supplier is responsible for defining a point on the module case where the temperature is measured.
This should be a point connected to an internal component with the least thermal margin, e.g., a laser diode. It
is recommended that the defined point on the module case be behind the equipment faceplate to
enable in-system monitoring. 10

10.1 Thermal Requirements ‌
The module case temperature may be within one or more of the case temperatures ranges defined in Table
29. The temperature ranges are applicable between 60 m below sea level and 1800m above sea level,
utilizing the host systems designed airflow. For further information see Telcordia GR-63-CORE, Issue 5,

15 December 2017, NEBSTM Requirements: Physical Protection. 16

17 Table 29- Temperature Range Class of operation

Class	Module Case Temperature
Standard	0°C through 70°C
Extended	-5°C through 85°C
Industrial	-40°C through 85°C

10.2 Thermal Requirements – tighter controlled environments ‌
The classes in Table 30 are intended for tighter controlled environments, e.g. data center environments as
described in “Thermal guidelines for data processing environments”, fourth Ed., ASHRAE, 2015. The four
classes correspond to different ranges of equipment intake air temperature. 23

25 Table 30- Temperature Range Classes for Tighter Controlled Applications

Class	Module Functional Case Temperature1	Module Case Temperature2
A1	15°C to 62°C	25°C to 62°C
A2	10°C to 65°C	20°C to 65°C
A3	5°C to 70°C	15°C to 70°C
A4	5°C to 75°C	15°C to 75°C
Notes: Functional includes all features available in Low Power Mode. Module case temperature means all specifications are met in high power mode.

10.3 External Case and Handle Touch Temperature ‌
For all power classes, all module case and handle surfaces outside of the cage must comply with applicable
touch temperature requirements. If the module case temperature will exceed applicable short-term touch
temperature limits, a means must be provided to prevent contact with the case during unlatching and removal.
Figure 44 and Appendix B show typical handles used to unlatch and remove the module, thereby limiting
contact with the module case. Handles are typically low thermal conductivity elastomer and allow for a higher
touch temperature, see IEC/UL 60950-1 [9] and Telcordia GR-63-CORE [24].

Appendix A Normative Module and Connector Performance Requirements ‌
A.1 QSFP-DD/QSFP-DD800 Performance Tables ‌
EIA-364-1000 [7] shall be used to define the test sequences and procedures for evaluating the QSFP-
DD/QSFP-DD800 connector systems described in this document. Where multiple test options are available,
the manufacturer shall select the appropriate option where not previously specified. The selected procedure
should be noted when reporting data. If there are conflicting requirements or test procedures between EIA-364
procedures and those contained within this document, this document shall be considered the prevailing
authority. Unless otherwise specified, procedures for sample size, data, and collection to be followed as

specified in EIA-364-1000. See EIA-364-1000 Annex B for objectives of tests and test groups. 10

This document represents the minimum requirements for the defined product. Additional test conditions and
evaluations may be conducted within the defined EIA-364-1000 sequences. More extreme test conditions and
failure criteria may be imposed and still meet the requirements of this document.
A.2 Test ‌
Table 31 summarizes the performance criteria that are to be satisfied by the connector described in this
document. Most performance criteria are validated by EIA-364-1000 testing, but this test suite leaves some
test details to be determined. To ensure that testing is repeatable, these details are identified in Table 32.
Finally, testing procedures used to validate any performance criteria not included in EIA-364-1000 are provided
in Table 33.

2 Table 31- Form Factor Performance Requirements

Performance Parameters	Description/ Details	Requirements
Mechanical/ Physical Tests
Plating Type	Plating type on connector contacts	Precious (refer to 7.5 for plating details)
Surface Treatment	Surface treatment on connector contacts; if surface treatment is applied, Test Group 6 is required	Manufacturer to specify
Wipe length	Designed distance a contact traverses over a mating contact surface during mating and resting at a final position. If less than 0.127 mm, test group 6 is required	Manufacturer to specify
Rated Durability Cycles	The expected number of durability cycles a component is expected to encounter over the course of its life	Connector/ cage: 100 cycles Module: 50 cycles
Mating Force1	Amount of force needed to mate a module with a connector when latches are deactivated	QSFP module: 60 N MAX QSFP-DD module: 90 N MAX
Unmating Force1	Amount of forced needed to separate a module from a connector when latches are deactivated	QSFP module: 30 N MAX QSFP-DD module: 50 N MAX
Latch Retention1	Amount of force the latching mechanism can withstand without unmating	QSFP module: 90 N MIN QSFP-DD module: 90 N MIN
Cage Latch Strength1	The amount of force that the cage latches can hold without being damaged.	125 N MIN
Cage Retention to Host Board1	Amount of force a cage can withstand without separating from the host board	114 N MIN
Environmental Requirements
Field Life	The expected service life for a component	10 years
Field Temperature2	The expected service temperature for a component	65°C
Electrical Requirements
Current	Maximum current to which a contact is exposed in use	0.5 A per signal contact MAX 1.5 A per power contact MAX
Operating Rating Voltage	Maximum voltage to which a contact is exposed in use	30 V DC per contact MAX
Note:

These performance criteria are not validated by EIA-364-1000 testing, see Table 33 for test procedures and pass/fail criteria.
Field temperature is the ambient air temperature around the component.

Table 32 describes the details necessary to perform the tests described in the EIA-364-1000 test sequences.
Testing shall be done in accordance with EIA-364-1000 and the test procedures it identifies in such a way that
the parameters/ requirements defined in Table 31 are met. Any information in this table supersedes EIA-364-
1000.

6 Table 32- EIA-364-1000 Test Details

Performance Parameters	Description/ Details	Requirements
Mechanical/ Physical Tests
Durability (preconditioning)	EIA-364-09 To be tested with connector, cage, and module. Latches may be locked out to aid in automated cycling.	No evidence of physical damage
Durability1	EIA-364-09 To be tested with connector, cage, and module. Latches may be locked out to aid in automated cycling.	No visual damage to mating interface or latching mechanism
Environmental Tests
Cyclic Temperature and Humidity	EIA-364-31 Method IV omitting step 7a Test Duration B	No intermediate test criteria
Vibration	EIA-364-28 Test Condition V Test Condition Letter C Test set-up: Connectors may be restrained by a plate that replicates the system panel opening as defined in this specification. External cables may be constrained to a non-vibrating fixture a minimum of 8 inches from the module. For cabled connector solutions: Wires may be attached to PCB or fixed to a non-vibrating fixture.	No evidence of physical damage -AND- No discontinuities longer than 1 μs allowed
Mixed Flowing Gas	EIA-364-65 Class II See Table 4.1 in EIA-364-1000 for exposure times Test option Per EIA-364-1000 option 3	No intermediate test criteria
Electrical Tests
Low Level Contact Resistance2	EIA-364-23 20 mV DC Max, 100 mA Max To include wire termination or connector-to-board termination	20 mΩ Max change from baseline
Dielectric Withstanding Voltage	EIA-364-20 Method B 300 VDC minimum for 1 minute Applied voltage may be product / application specific	No defect or breakdown between adjacent contacts -AND- 1 mA Max Leakage Current
Notes:

If the durability requirement on the connector is greater than that of the module, modules may be replaced after their specified durability rating.
The first low level contact resistance reading in each test sequence is used to determine a baseline measurement. Subsequent measurements in each sequence are measured against this baseline.

Table 33 describes the testing procedures necessary to validate performance criteria not validated by EIA-364-
1000 testing. The tests are to be performed in such a way that the parameters/ requirements defined in Table
31 are met.

5 Table 33- Additional Test Procedures

Tests	Test Descriptions and Details	Pass/ Fail Criteria
Mechanical/ Physical Tests
Mating Force1	EIA-364-13 To be tested with cage, connector, and module. Latching mechanism deactivated (locked out).	Refer to Table 31 -AND- No physical damage to any components
Unmating Force1
Latch Retention1	EIA-364-13 To be tested with cage, connector, and module. Latching mechanism engaged (not locked out).
Latch Strength	An axial load applied using a static load or ramped loading to the specified load. To be tested with cage, connector, and module or module representative tool without heat sinks Latching mechanism engaged (not locked out).
Cage Retention to Host Board	Tested with module, module analog, or fixtures mated to cage. Pull cage in a direction perpendicular to the board at a rate of 25.4mm/min to the specified force.	No physical damage to any components -AND- Cage shall not separate from board
Electrical Tests
Current	EIA-364-70 Method 3, 30-degree temperature rise Contacts energized: All signal and power contacts energized simultaneously	Refer to Table 31 for current magnitude
Note:
1. Values listed in Table 31 apply with or without the presence of a riding heat sink.

Appendix B Informative overall module length with elastomeric handle ‌
Figure 102 and Figure 103 show flexible elastomeric handles attached to the QSFP-DD/QSFP-DD800 module
latches (13.5 mm REF is the height of latch and not the heartsink). Handle ends for Types 1, Type 2A, and,
Type 2B modules should be aligned independent of module case extension. Type 1 modules should meet the
overall length of 118 mm maximum per Figure 102 with a handle length of approximately 50mm. Type 2
modules should comply with Figure 103 and have reduced handle length equal to the module case length
extension.

Figure 102: Informative overall module length with handle for Type 1 module

13 Figure 103: Informative overall module length with handle for Type 2A and Type 2B modules

Appendix C Informative QSFP-DD/QSFP-DD800 module heat sink Type 2A and 2B examples ‌
This appendix contains several designs examples of higher power Type 2A and 2B QSFP-DD/QSFP-DD800
with integrated nose heat sinks. 4

Thermal design is system dependent; however, systems seeking to maximize the benefit of the external heat
sink of Type 2A and 2B modules should consider minimizing bypass of airflow through the external heat sink.
Type 2A and 2B modules have a heatsink on the nose of the module. The QSFP-DD800 type 2B modules are
taller and can only be used in QSFP-DD800 stack cages as the ports on a stacked QSFP-DD800 cage are
separated by 1.7 mm more than QSFP-DD cages in section 7.7. However, a Type 2A module can be used in
all hosts.

One potential method is to use a minimal gap between the outer surface of the front panel and the trailing edge
of the external heat sink fins as shown in this appendix. Type 2A and 2B example modules insertion are
shown in Figure 104. Type 2A and Type 2B examples of 1X1 bezel design are shown in Figure 105. Example
of 2X1 bezel design is shown in Figure 106. Type 2A and Type 2B extruded heat sink examples are shown in
Figure 107. Type 2A and Type 2B die cast heat sinks with metal cover examples are shown in Figure 108.
Type 2A and Type 2B zipper fin heat sink examples are shown in Figure 109. 18

Dimensions A, B, and C for Type 2A and 2B heat sinks in Figure 106, Figure 107, Figure 108, and Figure 109
are given in Table 34. All dimensions shall have dimension tolerance of +/-0.1 mm. 21

22 Table 34- Dimensions for QSFP-DD/QSFP-DD800 and Module Type 2A/2B

Module Type	Dimension A	Dimensions	Module Type 2A	Module Type 2B
QSFP-DD	25.7 mm	B (max)	3.4 mm	5.1 mm
QSFP-DD800	27.83 mm	C (REF)	13.5 mm	15.2 mm

47.5

0.7 REF

3 Figure 104: Example of single and dual stacked QSFP-DD/QSFP-DD800 module insertions

2 Figure 105: Type 2A and 2B example of 1X1 bezel design

2 Figure 106: Type 2A and 2B example of 2X1 bezel design‌

ALLOW CLEARANCE FOR AIR FLOW

22 MIN

48. +0.2

2 0

8.5 ±0.1

EXTRUDED HEAT SINK

1.6 MAX

18.35 REF

0.4 REF (11X)

0.4 REF

3.9 REF

10 VENT HOLES 0.4 REF

SECTION A-A

SCALE 5/1

2 Figure 107: Example of extruded Heat Sink‌

22 MIN

48. +0.2

2 0

A B C

SHEET METAL

COVER

A 1.6 MAX

18.85

SEE DETAIL 1

0.25

(METAL COVER THICKNESS)

0.65

8.5 ±0.1

DIE CAST HEAT SINK

3.25

R0.3

11 DIE CAST

FINS

18.35

SECTION A-A

SCALE 5/1

0.8

DETAIL 1

SCALE 10/1

3 Figure 108: Example of die Cast Heat Sink with Metal Cover

ALLOW CLEARANCE FOR AIR FLOW

22 MIN

48. +0.2

2 0

A B

1.6 MAX C

8.5 ±0.1

0.3

18.35

0.3 (11X)

ZIPPER FINS

3.1

10 VENT HOLES

SECTION A-A

SCALE 5/1

3 Figure 109: Example of zipper Fin Heat Sink

Appendix D QSFP-DD800 Cage and Heat Sink Mechanism and EMI fingers ‌
This Annex details is an optional QSFP-DD800 compliant cage design which can provide improved EMI and
thermal performance. Implementation of this option does not require a change to the host PCB layout, front
panel cutout or the module. 6

D.1 Introduction ‌
The QSFP-DD800 cage design is an integral element of the EMI and thermal design strategy in QSFP-DD800
based architectures. In this annex a cage design is described with features specifically targeting these design
elements. The key features are as follows:
a) A dual row EMI spring clip which has been shown to enhance the shielding performance of the cage
b) A heat sink attach mechanism which has been shown to enhance the heat dissipation properties of the
module when inserted into the cage. 14

15 D.2 Mechanical Definition‌

16 D.3 EMI Spring Clip‌

17 Figure 110 illustrates the connection of the transceiver to the front panel using a dual contact EMI spring clip.

18 The additional connection provided by path #2 in Figure 110 serves to reduce the transfer impedance of this

19 connection resulting in improved shielding performance. Figure 111 shows the detail of the EMI spring clip. 20

21 Figure 110: Dual grounding path for EMI spring clip

24 Figure 111: EMI spring clip

D.4 Heat Sink Attach Mechanism ‌
A cage and heat sink attached mechanism is shown in Figure 112 and Figure 113. This cage implementation
maximizes the heat sink surface area and the corresponding module heat dissipation. This cage design relies
on integrated heat sink clips at the front and rear of the cage. This approach reduces part count and allows for
the use of a heat sink that is the full length of the cage. This cage design also incorporates an EMI latch
shield. This optional shield covers an aperture in the cage due to the latching mechanism resulting in
improved shielding performance. 8

10 Figure 112: Cage with integrated heat sink clips and EMI latch shield

D.5 Host PCB Layout ‌‌

Figure 113: 1xn cage (side view)
The features identified in this Annex do not impact the host PCB layout. Footprint compatibility permits the
cage implementation in the Annex to be applied in designs with more challenging EMI and thermal objectives.
D.6 Front Panel Cutout ‌
The EMI spring clip and cage design does not require a change to the front panel cutout allowing for
mechanical design compatibility between different cage options. 21

Appendix E Informative QSFP-DD800 2x1 Cabled Connector and Cage ‌
This Annex details is an optional QSFP-DD800 compliant cage design which can provide improved EMI and
thermal performance. Implementation of this option does not require a change to the host PCB layout, front
panel cutout or the module. 5

E.1 2x1 Cabled Upper Connector/Cage ‌
The 2x1 mechanical outline for the 100 Gb/s cabled connector/cage contains an upper cabled port and a lower
SMT port. The lower SMT port is identical to the 1x1 connector/cage in section 8.4. The upper
connector/cage contains low speed and power contacts that are press fit to the PCB and high-speed signal
contacts that are connected to cables. The cables are routed from the upper connector cage port to the host
ASIC. This specification does not define the cable construction or the near ASIC connection. The
connector/cage defined in this section is illustrated in Figure 114. All pluggable modules and direct attach
cable plugs (Type 1, Type 2, Type 2A, and Type 2B) must mate to the connectors and cages defined in this
specification.

19 Figure 114: 2x1 Cabled upper connector/cage

E.2 2x1 cabled connector/cage Electrical Connector Mechanical ‌
The 2x1 stacked cabled cage is illustrated in Figure 115. Figure 116 shows the stacked connector placement
over the surface mount lower connector. Figure 117 shows the lower surface mount connector attached to the
host PCB, the upper cabled connector and the 2x1 cage placement prior to press fit into the host PCB. Cabled
cage and connector detailed drawings are shown in Figure 119 and Figure 120. 6

11 Figure 115: 2x1 Cabled upper connector/cage illustration

5 Figure 116: Cabled upper connector over existing surface mount connector

2 Figure 117: Lower SMT connector, upper press fit connector, and the 2x1 cage

QSFP-DD800 Cabled Upper Connector

5 Figure 118: 2x1 Cabled over SMT connector and cage - Top View

2 Figure 119: 2x1 Cabled over SMT connector and cage – Side View

5 Figure 120: Cabled upper connector and surface mount connector dimensions

E.3 2x1 Cabled Connector and Cage host PCB layout ‌
A typical host board mechanical layout for attaching the QSFP-DD800 2x1 stacked cabled Connector and
Cage system is shown in Figure 121, however this is only a recommendation. The location of the pattern on
the host board is application specific. To achieve 112 Gbps performance pad dimensions and associated
tolerances must be adhered to and attention paid to the host board layout. The upper QSFP-DD800 cabled
non high-speed contacts are press fitted into host board as shown in Figure 121, for low speed signals and
Gnd/Vcc contact mapping see Figure 2. Cage system ground and power must be provided through the press-
fit pins or dedicated cable power delivery and not through the cable shield. 9

10 Host PCB requirements notes:

4 Figure 121: 2x1 Cabled upper connector/cage host board connector contacts

End of Document

Website:

Limitation on use of Information:

Permissions:

Dedication:

Foreword

2.4 Document Source

This Specification covers the following items:

Module Card Edge (Host Side)

(Module Side)

Top PCB viewed from top

(Module Side)

Bottom PCB viewed from bottom

Module Card Edge (Host Side)

Classic QSFP+/QSFP28/QSFP112 Pads

Additional

QSFP-DD/QSFP-DD800 Pads

Table 6- ePPS RF or Clock Frequency Reporting (Optional)

Figure 9: Instantaneous and sustained peak currents for Icc Host (see Table 13)

Top PCB viewed from top

Module Card Edge (Host Side)

(Module Side)

Bottom PCB viewed from bottom

Module Card Edge (Host Side)

(Module Side)

Classic QSFP+/QSFP28/QSFP112 Pads

Figure 24: Instantaneous and sustained peak currents for Icc Host (see Table 13)