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Arista Compatible

QDD-400G-LR4-A-FL Arista QDD-400G-LR4 Compatible 400GBase-LR4 QSFP56-DD 1271/1291/1311/1331nm 10km DOM Duplex LC SMF Optical Transceiver Module

$899.99

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Quick Specs

Rate Category
400G
Form Factor
QSFP-DD
Interface Type
400G-LR4-10
Standard / Protocol
100G Lambda MSA 400G-LR4-10; IEEE 802.3bs 400GAUI-8; QSFP-DD MSA
TX Wavelength
1271/1291/1311/1331nm (CWDM)
RX Wavelength
1271/1291/1311/1331nm (CWDM)
Cable Type
SMF
Reach
10km (SMF) with host FEC
DDM
Supported
Connector Type
Duplex LC
Power Consumption
12W max
Operating Temperature
0°C to +70°C (COM)

Overview

The QDD-400G-LR4-A-FL is a 400Gb/s Quad Small Form Factor Pluggable-double density (QSFP56-DD) optical module designed for 10km optical communication applications. The module converts 8 channels of 50Gb/s (PAM4) electrical input data to 4 channels of CWDM optical signals, and multiplexes them into a single channel for 400Gb/s optical transmission. Reversely, on the receiver side, the module optically de-multiplexes a 400Gb/s optical input into 4 channels of CWDM optical signals and converts them to 8 channels of 50Gb/s (PAM4) electrical output data.

Applications

  • 400G Ethernet over duplex single-mode fiber up to 10 km
  • Data center interconnect and campus links
  • Enterprise networking

Features

  • QSFP-DD MSA compliant (Type 2), hot-pluggable
  • 100G Lambda MSA 400G-LR4-10 specification compliant
  • 8 × 53.125 Gb/s PAM4 electrical interface (400GAUI-8)
  • 4 CWDM lanes at 1271/1291/1311/1331 nm, 106.25 Gb/s PAM4 per lane, with MUX/DEMUX
  • Up to 10 km over single-mode fiber with host FEC
  • Duplex LC connector
  • Average launch power −2.8 to +4.0 dBm per lane; stressed receiver sensitivity −4.1 dBm (OMAouter)
  • Digital diagnostic monitoring
  • Single +3.3V power supply, 12 W maximum power consumption
  • Operating case temperature: 0°C to +70°C (COM)
  • RoHS compliant, Class 1 laser product
  • 100% compatible with and programmed for the target OEM platform
  • Backed by a FluxLight lifetime warranty

Functional Description

The module incorporates 4 independent channels on CWDM4 1271/1291/1311/1331nm center wavelength, operating at 100G per channel. The transmitter path incorporates a quad channel EML driver and EML lasers together with an optical multiplexer. On the receiver path, an optical de-multiplexer is coupled to a 4 channel photodiode array. A DSP basis gearbox is used to convert 8 channels of 25GBaud PAM4 signals into 4 channels of 50GBaud PAM4 signals and also an 8-channel retimer and FEC block are integrated in this DSP. The electrical interface is compliant with IEEE 802.3bs and QSFP-DD MSA in the transmitting and receiving directions, and the optical interface is compliant to the 100G Lambda MSA 400G-LR4-10 specification with duplex LC connector.

Transceiver Block Diagram

Figure 1. Transceiver Block Diagram
Figure 1. Transceiver Block Diagram

Pin Assignment and Description

The electrical pinout of the QSFP-DD module is shown in Figure 2 below.

QDD-400G-LR4-A-FL Pin Assignment and Description
QDD-400G-LR4-A-FL Pin Assignment and Description
Pin #LogicSymbolDescriptionPlug SequenceNotes
1GNDGround1B1
2CML-ITx2nTransmitter Inverted Data Input3B
3CML-ITx2pTransmitter Non-Inverted Data Input3B
4GNDGround1B1
5CML-ITx4nTransmitter Inverted Data Input3B
6CML-ITx4pTransmitter Non-Inverted Data Input3B
7GNDGround1B1
8LVTTL-IModSelLModule Select3B
9LVTTL-IResetLModule Reset3B
10VccRx+3.3V Power Supply Receiver2B2
11LVCMOS-I/OSCL2-wire serial interface clock3B
12LVCMOS-I/OSDA2-wire serial interface data3B
13GNDGround1B1
14CML-ORx3pReceiver Non-Inverted Data Output3B
15CML-ORx3nReceiver Inverted Data Output3B
16GNDGround1B1
17CML-ORx1pReceiver Non-Inverted Data Output3B
18CML-ORx1nReceiver Inverted Data Output3B
19GNDGround1B1
20GNDGround1B1
21CML-ORx2nReceiver Inverted Data Output3B
22CML-ORx2pReceiver Non-Inverted Data Output3B
23GNDGround1B1
24CML-ORx4nReceiver Inverted Data Output3B
25CML-ORx4pReceiver Non-Inverted Data Output3B
26GNDGround1B1
27LVTTL-OModPrsLModule Present3B
28LVTTL-OIntLInterrupt3B
29VccTx+3.3V Power supply transmitter2B2
30Vcc1+3.3V Power supply2B2
31LVTTL-IInitModeInitialization Mode (called LPMode in legacy QSFP applications)3B
32GNDGround1B1
33CML-ITx3pTransmitter Non-Inverted Data Input3B
34CML-ITx3nTransmitter Inverted Data Input3B
35GNDGround1B1
36CML-ITx1pTransmitter Non-Inverted Data Input3B
37CML-ITx1nTransmitter Inverted Data Input3B
38GNDGround1B1
39GNDGround1A1
40CML-ITx6nTransmitter Inverted Data Input3A
41CML-ITx6pTransmitter Non-Inverted Data Input3A
42GNDGround1A1
43CML-ITx8nTransmitter Inverted Data Input3A
44CML-ITx8pTransmitter Non-Inverted Data Input3A
45GNDGround1A1
46ReservedFor future use3A3
47VS1Module Vendor Specific 13A3
48VccRx13.3V Power Supply2A2
49VS2Module Vendor Specific 23A3
50VS3Module Vendor Specific 33A3
51GNDGround1A1
52CML-ORx7pReceiver Non-Inverted Data Output3A
53CML-ORx7nReceiver Inverted Data Output3A
54GNDGround1A1
55CML-ORx5pReceiver Non-Inverted Data Output3A
56CML-ORx5nReceiver Inverted Data Output3A
57GNDGround1A1
58GNDGround1A1
59CML-ORx6nReceiver Inverted Data Output3A
60CML-ORx6pReceiver Non-Inverted Data Output3A
61GNDGround1A1
62CML-ORx8nReceiver Inverted Data Output3A
63CML-ORx8pReceiver Non-Inverted Data Output3A
64GNDGround1A1
65NCNo Connect3A3
66ReservedFor future use3A3
67VccTx13.3V Power Supply2A2
68Vcc23.3V Power Supply2A2
69ReservedFor Future Use3A3
70GNDGround1A1
71CML-ITx7pTransmitter Non-Inverted Data Input3A
72CML-ITx7nTransmitter Inverted Data Input3A
73GNDGround1A1
74CML-ITx5pTransmitter Non-Inverted Data Input3A
75CML-ITx5nTransmitter Inverted Data Input3A
76GNDGround1A1
  1. QSFP-DD uses common ground (GND) for all signals and supply (power). All are common within the QSFP-DD module and all module voltages are referenced to this potential unless otherwise noted. Connect these directly to the host board signal common ground plane.
  2. VccRx, VccRx1, Vcc1, Vcc2, VccTx and VccTx1 shall be applied concurrently. VccRx, VccRx1, Vcc1, Vcc2, VccTx and VccTx1 may be internally connected within the module in any combination. The connector Vcc pins are each rated for a maximum current of 1000 mA.
  3. All Vendor Specific, Reserved and No Connect pins may be terminated with 50 ohms to ground on the host. Pad 65 (No Connect) shall be left unconnected within the module. Vendor specific and Reserved pads shall have an impedance to GND that is greater than 10 kohms and less than 100 pF.

Absolute Maximum Ratings

It has to be noted that the operation in excess of any individual absolute maximum ratings might cause permanent damage to this module.

ParameterSymbolMinMaxUnits
Storage TemperatureTS-4085°C
Operating Case TemperatureTOP070°C
Power Supply VoltageVCC-0.53.6V
Relative Humidity (non-condensation)RH085%
Damage Threshold, each LaneTHd5.0dBm

Electrical Characteristics

The following electrical characteristics are defined over the Recommended Operating Environment unless otherwise specified.

ParameterTest PointMinTypicalMaxUnitsNotes
Power Consumption12W
Supply CurrentIcc3.64A
Transmitter (each Lane)
Signaling Rate, each LaneTP126.5625 ± 100 ppmGBd
Differential pk-pk Input Voltage ToleranceTP1a900mVpp1
Differential Termination MismatchTP110%
Differential Input Return LossTP1IEEE 802.3-2015 Equation (83E-5)dB
Differential to Common Mode Input Return LossTP1IEEE 802.3-2015 Equation (83E-6)dB
Module Stressed Input TestTP1aSee IEEE 802.3bs 120E.3.4.12
Single-ended Voltage Tolerance RangeTP1a-0.43.3V
DC Common Mode Input VoltageTP1-3502850mV3
Receiver (each Lane)
Signaling Rate, each laneTP426.5625 ± 100 ppmGBd
Differential Peak-to-Peak Output VoltageTP4900mVpp
AC Common Mode Output Voltage, RMSTP417.5mV
Differential Termination MismatchTP410%
Differential Output Return LossTP4IEEE 802.3-2015 Equation (83E-2)dB
Common to Differential Mode Conversion Return LossTP4IEEE 802.3-2015 Equation (83E-3)dB
Transition Time, 20% to 80%TP49.5ps
Near-end Eye Symmetry Mask Width (ESMW)TP40.265UI
Near-end Eye Height, DifferentialTP470mV
Far-end Eye Symmetry Mask Width (ESMW)TP40.2UI
Far-end Eye Height, DifferentialTP430mV
Far-end Pre-cursor ISI RatioTP4-4.52.5%
Common Mode Output Voltage (Vcm)TP4-3502850mV3
  1. With the exception to IEEE 802.3bs 120E.3.1.2 that the pattern is PRBS31Q or scrambled idle.
  2. Meets BER specified in IEEE 802.3bs 120E.1.1.
  3. DC common mode voltage generated by the host. Specification includes effects of ground offset voltage.

Optical Characteristics

ParameterSymbolMinTypicalMaxUnitsNotes
Wavelength AssignmentL01264.512711277.5nm
L11284.512911297.5nm
L21304.513111317.5nm
L31324.513311337.5nm
Transmitter
Data Rate, each Lane53.125 ± 100 ppmGBd
Modulation FormatPAM4
Side-mode Suppression RatioSMSR30dB
Total Average Launch PowerPT10.0dBm
Average Launch Power, each LanePAVG-2.84.0dBm1
Outer Optical Modulation Amplitude (OMAouter), each LanePOMA0.24.2dBm2
Launch Power in OMAouter minus TDECQ, each Lane, for ER ≥ 4.5 dB-1.2dBm
Launch Power in OMAouter minus TDECQ, each Lane, for ER < 4.5 dB-1.1dBm
Transmitter and Dispersion Eye Closure for PAM4, each LaneTDECQ3.9dB
TDECQ – 10*log10(Ceq), each Lane3.9dB3
Extinction RatioER3.5dB
Difference in Launch Power between any Two Lanes (OMAouter)4dB
RIN15.6OMARIN-136dB/Hz
Optical Return Loss ToleranceTOL15.6dB
Transmitter ReflectanceRT-26dB
Transmitter Transition Time17ps
Average Launch Power of OFF Transmitter, each LanePoff-20dBm
Receiver
Data Rate, each Lane53.125 ± 100 ppmGBd
Modulation FormatPAM4
Damage Threshold, each LaneTHd5.0dBm5
Average Receive Power, each Lane-9.14.0dBm4
Receive Power (OMAouter), each Lane4.2dBm
Difference in Receiver Power between any Two Lanes (OMAouter)4.6dB
Receiver Sensitivity (OMAouter), each LaneSENmax(−6.6, SECQ − 8.0)dBm6
Stressed Receiver Sensitivity (OMAouter), each LaneSRS-4.1dBm7
Receiver ReflectanceRR-26dB
LOS AssertLOSA-20dBm
LOS De-assertLOSD-12.1dBm
LOS HysteresisLOSH0.5dB
Stressed Conditions for Stressed Receiver Sensitivity
Stressed Eye Closure for PAM4 (SECQ), Lane under Test3.9dB
SECQ – 10*log10(Ceq), Lane under Test3.9dB
OMAouter of each Aggressor Lane0.5dBm
  1. Average launch power, each lane (min) is informative and not the principal indicator of signal strength. A transmitter with launch power below this value cannot be compliant; however, a value above this does not ensure compliance.
  2. Even if the TDECQ < 1.4 dB for an extinction ratio of ≥ 4.5 dB or TDECQ < 1.3 dB for an extinction ratio of < 4.5 dB, the OMAouter (min) must exceed the minimum value specified here.
  3. Ceq is a coefficient defined in IEEE Std 802.3-2018 clause 121.8.5.3 which accounts for reference equalizer noise enhancement.
  4. Average receive power, each lane (min) is informative and not the principal indicator of signal strength. A received power below this value cannot be compliant; however, a value above this does not ensure compliance.
  5. The receiver shall be able to tolerate, without damage, continuous exposure to an optical input signal having this average power level.
  6. Receiver sensitivity (OMAouter), each lane (max) is informative and is defined for a transmitter with a value of SECQ up to 3.9 dB. It should meet Equation (1), which is illustrated in Figure 4: RS = max(−6.6, SECQ − 8.0) dBm (1), where RS is the receiver sensitivity and SECQ is the SECQ of the transmitter used to measure the receiver sensitivity.
  7. Measured with conformance test signal at TP3 for the BER equal to 2.4x10-4.
  8. These test conditions are for measuring stressed receiver sensitivity. They are not characteristics of the receiver.
Figure 4. Illustration of Receiver Sensitivity Mask for 400G-
Figure 4. Illustration of Receiver Sensitivity Mask for 400G-

Digital Diagnostic Functions

The following digital diagnostic characteristics are defined over the normal operating conditions unless otherwise specified.

ParameterSymbolMinMaxUnitsNotes
Temperature monitor absolute errorDMI_Temp-33°COver operating temperature range
Supply voltage monitor absolute errorDMI_VCC-0.10.1VOver full operating range
Channel RX power monitor absolute errorDMI_RX_Ch-22dB1
Channel bias current monitor absolute errorDMI_Ibias_Ch-1010%
Channel TX power monitor absolute errorDMI_TX_Ch-22dB1
  1. Due to measurement accuracy of different single mode fibers, there could be an additional +/-1 dB fluctuation, or a +/- 3 dB total accuracy.

Mechanical Dimensions

Figure 5. Mechanical Outline
Figure 5. Mechanical Outline

ESD

This transceiver is specified as ESD threshold 1kV for high speed data pins and 2kV for all other electrical input pins, tested per MIL-STD-883, Method 3015.4 /JESD22-A114-A (HBM). However, normal ESD precautions are still required during the handling of this module. This transceiver is shipped in ESD protective packaging. It should be removed from the packaging and handled only in an ESD protected environment.

Laser Safety

This is a Class 1 Laser Product according to EN 60825-1:2014. This product complies with 21 CFR 1040.10 and 1040.11 except for deviations pursuant to Laser Notice No. 50, dated (June 24, 2007).

Caution: Use of controls or adjustments or performance of procedures other than those specified herein may result in hazardous radiation exposure.

The FluxLight QDD-400G-LR4-A-FL is compatible with the Arista QDD-400G-LR4, which Arista certifies on all its platforms. It works in any Arista switch port that takes the QDD-400G-LR4, running EOS 4.25.2 or later.

Licensing

The following is a list of Finisar Corporation patents Fluxlight has licensed. This licensure recognizes and compensates Finisar for their intellectual property. The QDD-400G-LR4-A-FL, like all Fluxlight optical transceivers, is covered by this license agreement. Therefore, Fluxlight customers can rest assured that all products purchased are fully licensed, and our customers are under no potential liability that may ensue from the use of unlicensed optical transceiver products.

U.S. Patent Numbers: 7,184,668 (System and method of protecting eye safety during operation of a fiber optic transceiver), 7,079,775 (Integrated memory mapped controller circuit for fiber optics transceiver), 6,957,021 (Optical transceiver with memory mapped locations), 7,058,310 (System and method for protecting eye safety during operation of a fiber optic transceiver), 6,952,531 (System and method for protecting eye safety during operation of a fiber optic transceiver), 7,162,160 (System and method for protecting eye safety during operation of a fiber optic transceiver), 7,050,720 (Integrated memory mapped controller circuit for fiber optics transceiver)

Original Equipment Manufacturer (OEM) names may be registered trademarks of the respective OEM, and the OEM has neither authorized nor sponsored the use of its trademark or trade name. All OEM names are used for cross reference/comparative purposes only.

Warranty

This part is covered by our Limited Lifetime Warranty, a 10-year serviceable lifetime, and our 30-Day Money-Back Guarantee. Read the full warranty and return terms.

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